library ieee;										--庫參考
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity MCUCPLD is									--設計實體
	port(PP		:in std_logic_vector(7 downto 0);	--端口說明，輸入端口
		PSel	:in std_logic_vector(1 downto 0);	--擴展端口選擇
		PA		:out std_logic_vector(7 downto 0);	--擴展輸出端口PA
		PB		:out std_logic_vector(7 downto 0);	--擴展輸出端口PB
		PC		:out std_logic_vector(7 downto 0);	--擴展輸出端口PC
		PD		:out std_logic_vector(7 downto 0));	--擴展輸出端口PD
end MCUCPLD;

architecture Arch of MCUCPLD is						--構造體
signal SA:std_logic_vector(7 downto 0);				--內部變量
signal SB:std_logic_vector(7 downto 0);
signal SC:std_logic_vector(7 downto 0);
signal SD:std_logic_vector(7 downto 0);

begin
	process(PSel,PP)								--過程語句
	begin
		if PSel="00" then							--選擇端口PA輸出
			SA<=PP;
		elsif PSel="01" then						--選擇端口PB輸出
			SB<=PP;
		elsif	PSel="10" then						--選擇端口PC輸出
			SC<=PP;
		else										--選擇端口PD輸出
			SD<=PP;
		end if;
		PA<=SA;										--端口輸出
		PB<=SB;
		PC<=SC;
		PD<=SD;
	end process;
end Arch;