?? icx229.v.bak
字號:
module ICX229(clk,rst,v1,v1h,v2,v3,v3h,v4,h1,h2,r,sub);//clk周期為8.73ns
input clk;
input rst;
output h1;
output h2;
output r;
output v2;
output v4;
output v1;
output v3;
output v1h;
output v3h;
output sub;
reg h1;
reg h2;
reg r;
reg v2;
reg v4;
reg v1;
reg v3;
reg v1h;
reg v3h;
reg sub;
reg [14:0]i;
reg [14:0]j;
reg [14:0]a;
reg [14:0]b;
reg [14:0]d;
reg [14:0]e;
reg [14:0]g;
reg [14:0]h;
reg [14:0]l;
reg [14:0]m;
reg [30:0]o;
reg [30:0]p;
reg [30:0]q;
reg [2:0]s;
reg [2:0]state;
reg [2:0]state0;
reg [2:0]state1;
reg [2:0]state2;
reg [2:0]state3;
reg [2:0]state4;
reg [2:0]state5;
reg [2:0]state7;
reg [2:0]state8;
reg [2:0]state10;
reg [2:0]state11;
reg [2:0]state13;
reg [2:0]state14;
reg [2:0]state16;
reg [2:0]state17;
reg [2:0]state18;
always@(posedge clk)
if(!rst)
begin
h1<=0;
h2<=1;
i<=0;
j<=0;
state<=0;
state0<=0;
state1<=0;
state2<=0;
end
else
case(state)
0:if(j==796)
case(state2)
0:begin
h1<=0;
h2<=1;
state2<=1;
end
1:begin
h1<=0;
h2<=1;
state2<=2;
end
2:begin
h1<=0;
h2<=1;
state2<=3;
end
3:begin
h1<=0;
h2<=1;
state2<=0;
state<=1;
j<=0;
end
endcase
else
begin
j<=j+1;
h1<=1;
h2<=0;
end
1:if(i==6528)
begin
state<=2;
i<=0;
h1<=1;
h2<=0;
end
else
case(state1)
0:begin
h1<=1;
h2<=0;
i<=i+1;
state1<=1;
end
1:begin
h1<=1;
h2<=0;
i<=i+1;
state1<=2;
end
2:begin
h1<=1;
h2<=0;
i<=i+1;
state1<=3;
end
3:begin
h1<=1;
h2<=0;
i<=i+1;
state1<=4;
end
4:begin
h1<=0;
h2<=1;
i<=i+1;
state1<=5;
end
5:begin
h1<=0;
h2<=1;
i<=i+1;
state1<=6;
end
6:begin
h1<=0;
h2<=1;
i<=i+1;
state1<=7;
end
7:begin
h1<=0;
h2<=1;
i<=i+1;
state1<=0;
end
endcase
2:if(j==795)
case(state0)
0:begin
h1<=0;
h2<=1;
state0<=1;
end
1:begin
h1<=0;
h2<=1;
state0<=2;
end
2:begin
h1<=0;
h2<=1;
state0<=3;
end
3:begin
h1<=0;
h2<=1;
state0<=0;
state<=1;
j<=0;
end
endcase
else
begin
j<=j+1;
h1<=1;
h2<=0;
end
endcase
always@(posedge clk)
if(!rst)
begin
r<=0;
s<=0;
state3<=0;
end
else
case(state3)
0:if(s==2)
begin
r<=0;
s<=0;
state3<=1;
end
else
begin
r<=1;
s<=s+1;
end
1:if(s==5)
begin
r<=1;
s<=0;
state3<=2;
end
else
begin
r<=0;
s<=s+1;
end
2:if(s==1)
begin
r<=0;
s<=0;
state3<=1;
end
else
begin
r<=1;
s<=s+1;
end
endcase
always@(posedge clk)
if(!rst)
begin
v2<=1;
state4<=0;
state5<=0;
a<=0;
b<=0;
end
else
case(state5)
0:if(b==12)
begin
state5<=1;
b<=0;
a<=0;
end
else
case(state4)
0:if(a==264)
begin
v2<=~v2;
a<=0;
state4<=1;
end
else
a<=a+1;
1:if(a==263)
begin
v2<=~v2;
a<=0;
state4<=2;
end
else
a<=a+1;
2:if(a==6799)
begin
a<=1;
state4<=0;
state5<=0;
b<=b+1;
end
else
a<=a+1;
endcase
1:case(state4)
0:if(a==263)
begin
v2<=~v2;
a<=0;
state4<=1;
end
else
a<=a+1;
1:if(a==263)
begin
v2<=~v2;
a<=0;
state4<=2;
end
else
a<=a+1;
2:if(a==3931)
begin
v2<=~v2;
a<=0;
state4<=3;
end
else
a<=a+1;
3:if(a==1385)
begin
v2<=~v2;
a<=0;
state4<=4;
end
else
a<=a+1;
4:if(a==1481)
begin
a<=0;
state4<=0;
state5<=2;
end
else
a<=a+1;
endcase
2:if(b==311)
begin
state5<=3;
b<=0;
end
else
case(state4)
0:if(a==263)
begin
v2<=~v2;
a<=0;
state4<=1;
end
else
a<=a+1;
1:if(a==263)
begin
v2<=~v2;
a<=0;
state4<=2;
end
else
a<=a+1;
2:if(a==6803)
begin
a<=0;
state4<=0;
state5<=2;
b<=b+1;
end
else
a<=a+1;
endcase
3:case(state4)
0:if(a==263)
begin
v2<=~v2;
a<=0;
state4<=1;
end
else
a<=a+1;
1:if(a==263)
begin
v2<=~v2;
a<=0;
state4<=2;
end
else
a<=a+1;
2: if(a==3931)
begin
v2<=~v2;
a<=0;
state4<=3;
end
else
a<=a+1;
3:if(a==3395)
begin
v2<=~v2;
a<=0;
state4<=4;
end
else
a<=a+1;
4:if(a==6799)
begin
a<=0;
state4<=0;
state5<=4;
end
else
a<=a+1;
endcase
4:if(b==299)
begin
state5<=0;
b<=0;
a<=2;
end
else
case(state4)
0:if(a==263)
begin
v2<=~v2;
a<=0;
state4<=1;
end
else
a<=a+1;
1:if(a==263)
begin
v2<=~v2;
a<=0;
state4<=2;
end
else
a<=a+1;
2:if(a==6799)
begin
a<=0;
state4<=0;
state5<=4;
b<=b+1;
end
else
a<=a+1;
endcase
endcase
always@(posedge clk)
if(!rst)
begin
v4<=0;
state7<=0;
state8<=0;
d<=0;
e<=0;
end
else
case(state8)
0:if(e==324)
begin
state8<=1;
e<=0;
d<=0;
end
else
case(state7)
0:if(d==176)
begin
v4<=~v4;
d<=0;
state7<=1;
end
else
d<=d+1;
1:if(d==439)
begin
v4<=~v4;
d<=0;
state7<=2;
end
else
d<=d+1;
2:if(d==6711)
begin
d<=1;
state7<=0;
state8<=0;
e<=e+1;
end
else
d<=d+1;
endcase
1:case(state7)
0:if(d==175)
begin
v4<=~v4;
d<=0;
state7<=1;
end
else
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