Release 7.1.04i Map H.42Xilinx Mapping Report File for Design 'ICX229'Design Information------------------Command Line   : D:/Xilinx/bin/nt/map.exe -ise d:\test\icx229al\ICX229AL.ise
-intstyle ise -p xc3s400-pq208-4 -cm area -pr b -k 4 -c 100 -o ICX229_map.ncd
ICX229.ngd ICX229.pcf Target Device  : xc3s400Target Package : pq208Target Speed   : -4Mapper Version : spartan3 -- $Revision: 1.26.6.4 $Mapped Date    : Sat Jan 19 16:44:20 2008Design Summary--------------Number of errors:      0Number of warnings:    0Logic Utilization:  Number of Slice Flip Flops:         314 out of   7,168    4%  Number of 4 input LUTs:             883 out of   7,168   12%Logic Distribution:  Number of occupied Slices:                          586 out of   3,584   16%    Number of Slices containing only related logic:     586 out of     586  100%    Number of Slices containing unrelated logic:          0 out of     586    0%      *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:          1,113 out of   7,168   15%  Number used as logic:                883  Number used as a route-thru:         230  Number of bonded IOBs:               12 out of     141    8%    IOB Flip Flops:                     1  Number of GCLKs:                     1 out of       8   12%Total equivalent gate count for design:  9,237Additional JTAG gate count for IOBs:  576Peak Memory Usage:  118 MBNOTES:   Related logic is defined as being logic that shares connectivity - e.g. two   LUTs are "related" if they share common inputs.  When assembling slices,   Map gives priority to combine logic that is related.  Doing so results in   the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin packing   unrelated logic into a slice once 99% of the slices are occupied through   related logic packing.   Note that once logic distribution reaches the 99% level through related   logic packing, this does not mean the device is completely utilized.   Unrelated logic packing will then begin, continuing until all usable LUTs   and FFs are occupied.  Depending on your timing budget, increased levels of   unrelated logic packing may adversely affect the overall timing performance   of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:   BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP)INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.Section 4 - Removed Logic Summary---------------------------------   2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE 		BLOCKGND 		XST_GNDVCC 		XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| clk                                | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || h1                                 | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || h2                                 | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || r                                  | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       || rst                                | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || sub                                | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || v1                                 | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || v2                                 | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || v3                                 | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || v4                                 | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || v1h                                | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || v3h                                | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details--------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 12Number of Equivalent Gates for Design = 9,237Number of RPM Macros = 0Number of Hard Macros = 0DCIRESETs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DCMs = 0GCLKs = 1ICAPs = 018X18 Multipliers = 0Block RAMs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 16IOB Dual-Rate Flops not driven by LUTs = 0IOB Dual-Rate Flops = 0IOB Slave Pads = 0IOB Master Pads = 0IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 1IOB Flip Flops = 1Unbonded IOBs = 0Bonded IOBs = 12XORs = 230CARRY_INITs = 128CARRY_SKIPs = 0CARRY_MUXes = 230Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MUXFs = 12MULT_ANDs = 04 input LUTs used as Route-Thrus = 2304 input LUTs = 883Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 15Slice Flip Flops = 314SliceMs = 0SliceLs = 586Slices = 586F6 Muxes = 0F5 Muxes = 12F8 Muxes = 0F7 Muxes = 0Number of LUT signals with 4 loads = 23Number of LUT signals with 3 loads = 36Number of LUT signals with 2 loads = 71Number of LUT signals with 1 load = 675NGM Average fanout of LUT = 2.07NGM Maximum fanout of LUT = 32NGM Average fanin for LUT = 3.5878Number of LUT symbols = 883