library verilog;use verilog.vl_types.all;entity top is    port(        clk             : in     vl_logic;        rst             : in     vl_logic;        adcck           : out    vl_logic;        clkbp           : out    vl_logic;        clpdm           : out    vl_logic;        clpob           : out    vl_logic;        h1              : out    vl_logic;        h2              : out    vl_logic;        pblk            : out    vl_logic;        r               : out    vl_logic;        reset           : out    vl_logic;        sclk            : out    vl_logic;        sdata           : out    vl_logic;        shd             : out    vl_logic;        shp             : out    vl_logic;        sload           : out    vl_logic;        sub             : out    vl_logic;        v1              : out    vl_logic;        v1h             : out    vl_logic;        v2              : out    vl_logic;        v3              : out    vl_logic;        v3h             : out    vl_logic;        v4              : out    vl_logic    );end top;