library verilog;use verilog.vl_types.all;entity clk4 is    port(        clkin_in        : in     vl_logic;        clkin_ibufg_out : out    vl_logic;        clk0_out        : out    vl_logic;        clk2x_out       : out    vl_logic;        locked_out      : out    vl_logic    );end clk4;