?? test1_v.fdo
字號:
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Fri Jan 25 13:00:48 涓?鍥芥爣鍑嗘椂闂? 2008
##
vlib work
vlog VSP2232.v
vlog test1.v
vlog "D:/Xilinx/verilog/src/glbl.v"
vsim -t 1ps -L xilinxcorelib_ver -L unisims_ver -lib work test1_v glbl
do {test1_v.udo}
view wave
add wave *
view structure
view signals
run 1000ns
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -