Release 7.1.04i - xst H.42Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.47 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.47 s | Elapsed : 0.00 / 0.00 s --> Reading design: VSP2232.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "VSP2232.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "VSP2232"Output Format                      : NGCTarget Device                      : xc3s400-4-pq208---- Source OptionsTop Module Name                    : VSP2232Automatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 8Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : VSP2232.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yesenable_auto_floorplanning          : No==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "VSP2232.v"Module <VSP2232> compiledNo errors in compilationAnalysis of file <"VSP2232.prj"> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <VSP2232>.Module <VSP2232> is correct for synthesis.     Set property "resynthesize = true" for unit <VSP2232>.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <VSP2232>.    Related source file is "VSP2232.v".    Found finite state machine <FSM_0> for signal <t1>.    -----------------------------------------------------------------------    | States             | 2                                              |    | Transitions        | 3                                              |    | Inputs             | 2                                              |    | Outputs            | 2                                              |    | Clock              | clk (rising_edge)                              |    | Reset              | rst (negative)                                 |    | Reset type         | synchronous                                    |    | Reset State        | 0000                                           |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------    Found finite state machine <FSM_1> for signal <t2>.    -----------------------------------------------------------------------    | States             | 2                                              |    | Transitions        | 3                                              |    | Inputs             | 2                                              |    | Outputs            | 2                                              |    | Clock              | clk (rising_edge)                              |    | Reset              | rst (negative)                                 |    | Reset type         | synchronous                                    |    | Reset State        | 0000                                           |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------    Found finite state machine <FSM_2> for signal <t3>.    -----------------------------------------------------------------------    | States             | 3                                              |    | Transitions        | 6                                              |    | Inputs             | 1                                              |    | Outputs            | 3                                              |    | Clock              | clk (rising_edge)                              |    | Reset              | rst (negative)                                 |    | Reset type         | synchronous                                    |    | Reset State        | 0000                                           |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------    Found finite state machine <FSM_3> for signal <t4>.    -----------------------------------------------------------------------    | States             | 5                                              |    | Transitions        | 10                                             |    | Inputs             | 5                                              |    | Outputs            | 5                                              |    | Clock              | clk (rising_edge)                              |    | Reset              | rst (negative)                                 |    | Reset type         | synchronous                                    |    | Reset State        | 0000                                           |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------    Found finite state machine <FSM_4> for signal <t5>.    -----------------------------------------------------------------------    | States             | 3                                              |    | Transitions        | 6                                              |    | Inputs             | 3                                              |    | Outputs            | 3                                              |    | Clock              | clk (rising_edge)                              |    | Reset              | rst (negative)                                 |    | Reset type         | synchronous                                    |    | Reset State        | 0000                                           |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------    Found 1-bit register for signal <shp>.    Found 1-bit register for signal <adcck>.    Found 1-bit register for signal <clpdm>.    Found 1-bit register for signal <pblk>.    Found 1-bit register for signal <clpob>.    Found 1-bit register for signal <shd>.    Found 4-bit 4-to-1 multiplexer for signal <$n0033> created at line 83.    Found 4-bit adder for signal <$n0038> created at line 23.    Found 4-bit adder for signal <$n0039> created at line 53.    Found 15-bit adder for signal <$n0041> created at line 118.    Found 15-bit adder for signal <$n0042> created at line 169.    Found 4-bit adder for signal <$n0043>.    Found 4-bit register for signal <va>.    Found 4-bit register for signal <vb>.    Found 4-bit register for signal <vc>.    Found 15-bit register for signal <vd>.    Found 15-bit register for signal <ve>.    Summary:	inferred   5 Finite State Machine(s).	inferred  48 D-type flip-flop(s).	inferred   5 Adder/Subtractor(s).	inferred   4 Multiplexer(s).Unit <VSP2232> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Analyzing FSM <FSM_4> for best encoding.Optimizing FSM <FSM_4> on signal <t5[1:2]> with sequential encoding.------------------- State | Encoding------------------- 0000  | 00 0001  | 01 0010  | 10-------------------Analyzing FSM <FSM_3> for best encoding.Optimizing FSM <FSM_3> on signal <t4[1:5]> with speed1 encoding.------------------- State | Encoding------------------- 0000  | 10000 0001  | 01000 0010  | 00100