////////////////////////////////////////////////////////////////////////////////// Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.//////////////////////////////////////////////////////////////////////////////////   ____  ____//  /   /\/   /// /___/  \  /    Vendor: Xilinx// \   \   \/     Version: H.42//  \   \         Application: netgen//  /   /         Filename: shuju_timesim.v// /___/   /\     Timestamp: Tue Jan 15 12:22:54 2008// \   \  /  \ //  \___\/\___\//             // Command	: -intstyle ise -s 4 -pcf shuju.pcf -sdf_anno true -w -ofmt verilog -sim shuju.ncd shuju_timesim.v // Device	: 3s400pq208-4 (PRODUCTION 1.37 2005-07-22)// Input file	: shuju.ncd// Output file	: shuju_timesim.v// # of Modules	: 1// Design Name	: shuju// Xilinx	: D:/Xilinx//             // Purpose:    //     This verilog netlist is a verification model and uses simulation //     primitives which may not represent the true implementation of the //     device, however the netlist is functionally correct and should not //     be modified. This file cannot be synthesized and should only be used //     with supported simulation tools.//             // Reference:  //     Development System Reference Guide, Chapter 23//     Synthesis and Verification Design Guide, Chapter 6//             ////////////////////////////////////////////////////////////////////////////////`timescale 1 ns/1 psmodule shuju (  rst, sclk, sdata, zhuangtai, count, datain);  input rst;  input sclk;  output sdata;  output [4 : 0] zhuangtai;  output [4 : 0] count;  output [15 : 0] datain;  wire datain_4;  wire datain_5;  wire datain_6;  wire datain_7;  wire datain_8;  wire datain_9;  wire datain_10;  wire \sclk_BUFGP/IBUFG ;  wire datain_11;  wire datain_12;  wire zhuangtai_0;  wire datain_13;  wire zhuangtai_1;  wire datain_14;  wire GLOBAL_LOGIC0;  wire datain_15;  wire count_0;  wire count_1;  wire count_2;  wire count_3;  wire count_4;  wire sdata_OBUF;  wire rst_IBUF;  wire datain_3;  wire GLOBAL_LOGIC1;  wire sclk_BUFGP;  wire \_n0001<2>1/O ;  wire \_n0008_SW3/O ;  wire N175_0;  wire N75;  wire zhuangtai_0_1;  wire _n0008_0;  wire N26_0;  wire N200_0;  wire \_n0001<3>_SW2/O ;  wire N202_0;  wire N203_0;  wire \_n0001<4>_SW1/O ;  wire N11_0;  wire N71_0;  wire N180_0;  wire \_n0002<13>211_SW0/O ;  wire \_n0002<10>1_SW0/O ;  wire \Ker111_SW0/O ;  wire \_n0002<11>1_SW0/O ;  wire \_n0002<14>1_SW0/O ;  wire \_n0001<4>_SW0_SW1/O ;  wire zhuangtai_1_1;  wire N149_0;  wire \_n0002<15>1_SW0/O ;  wire N194_0;  wire \_n0008_SW8/O ;  wire zhuangtai_0_2;  wire N215_0;  wire \_n0002<5>1_SW0/O ;  wire \_n0002<6>1_SW0/O ;  wire \_n0003<0>_0 ;  wire N191_0;  wire \_n0008_SW6/O ;  wire N213_0;  wire \_n0002<8>16_SW1/O ;  wire \_n0002<9>1_SW0/O ;  wire N197_0;  wire \_n0008_SW10/O ;  wire N217_0;  wire \_n0002<13>5_SW0/O ;  wire GSR = glbl.GSR;  wire GTS = glbl.GTS;  wire \datain<4>/ENABLE ;  wire \datain<4>/O ;  wire \datain<5>/ENABLE ;  wire \datain<5>/O ;  wire \datain<6>/ENABLE ;  wire \datain<6>/O ;  wire \datain<7>/ENABLE ;  wire \datain<7>/O ;  wire \datain<8>/ENABLE ;  wire \datain<8>/O ;  wire \datain<9>/ENABLE ;  wire \datain<9>/O ;  wire \datain<10>/ENABLE ;  wire \datain<10>/O ;  wire \sclk/INBUF ;  wire \datain<11>/ENABLE ;  wire \datain<11>/O ;  wire \datain<12>/ENABLE ;  wire \datain<12>/O ;  wire \zhuangtai<0>/ENABLE ;  wire \zhuangtai<0>/O ;  wire \datain<13>/ENABLE ;  wire \datain<13>/O ;  wire \zhuangtai<1>/ENABLE ;  wire \zhuangtai<1>/O ;  wire \datain<14>/ENABLE ;  wire \datain<14>/O ;  wire \zhuangtai<2>/ENABLE ;  wire \zhuangtai<2>/O ;  wire \datain<15>/ENABLE ;  wire \datain<15>/O ;  wire \zhuangtai<3>/ENABLE ;  wire \zhuangtai<3>/O ;  wire \zhuangtai<4>/ENABLE ;  wire \zhuangtai<4>/O ;  wire \count<0>/ENABLE ;  wire \count<0>/O ;  wire \count<1>/ENABLE ;  wire \count<1>/O ;  wire \count<2>/ENABLE ;  wire \count<2>/O ;  wire \count<3>/ENABLE ;  wire \count<3>/O ;  wire N175;  wire N197;  wire N191;  wire N194;  wire N149;  wire \sdata_OBUF/REVUSED ;  wire \sdata_OBUF/DYMUX ;  wire \_n0000151/O ;  wire \sdata_OBUF/SRINVNOT ;  wire \sdata_OBUF/CLKINVNOT ;  wire \datain_15/DXMUX ;  wire \_n0002<15>1/O ;  wire \_n0002<15>1_SW0/O_pack_1 ;  wire \datain_15/SRINVNOT ;  wire \datain_15/CLKINVNOT ;  wire CHOICE743;  wire \_n0008_SW8/O_pack_1 ;  wire \datain_5/DXMUX ;  wire \_n0002<5>1/O ;  wire \_n0002<5>1_SW0/O_pack_1 ;  wire \datain_5/SRINVNOT ;  wire \datain_5/CLKINVNOT ;  wire \datain_6/DXMUX ;  wire \_n0002<6>1/O ;  wire \_n0002<6>1_SW0/O_pack_1 ;  wire \datain_6/SRINVNOT ;  wire \datain_6/CLKINVNOT ;  wire \zhuangtai_0/DXMUX ;  wire \zhuangtai_0/FXMUX ;  wire \zhuangtai_0/DYMUX ;  wire \_n0002<3>1/O ;  wire \zhuangtai_0/SRINVNOT ;  wire \zhuangtai_0/CLKINVNOT ;  wire N203;  wire \datain_4/REVUSED ;  wire \datain_4/DYMUX ;  wire \_n0002<4>161/O ;  wire \datain_4/SRINVNOT ;  wire \datain_4/CLKINVNOT ;  wire CHOICE767;  wire \_n0008_SW6/O_pack_1 ;  wire \datain_7/REVUSED ;  wire \datain_7/DYMUX ;  wire \_n0002<7>161/O ;  wire \datain_7/SRINVNOT ;  wire \datain_7/CLKINVNOT ;  wire \datain_8/DXMUX ;  wire \_n0002<8>16/O ;  wire \_n0002<8>16_SW1/O_pack_1 ;  wire \datain_8/SRINVNOT ;  wire \datain_8/CLKINVNOT ;  wire \datain_9/DXMUX ;  wire \_n0002<9>1/O ;  wire \_n0002<9>1_SW0/O_pack_1 ;  wire \datain_9/SRINVNOT ;  wire \datain_9/CLKINVNOT ;  wire \zhuangtai_1/REVUSED ;  wire \zhuangtai_1/DYMUX ;  wire \zhuangtai_1/GYMUX ;  wire N137;  wire \zhuangtai_1/SRINVNOT ;  wire \zhuangtai_1/CLKINVNOT ;  wire CHOICE751;  wire \_n0008_SW10/O_pack_1 ;  wire CHOICE736;  wire \_n0002<13>5_SW0/O_pack_1 ;  wire _n0008;  wire N75_pack_1;  wire N213;  wire N215;  wire N180;  wire N202;  wire N200;  wire N217;  wire \zhuangtai_0_1/DYMUX ;  wire \zhuangtai_0_1/SRINVNOT ;  wire \zhuangtai_0_1/CLKINVNOT ;  wire \zhuangtai_0_2/DYMUX ;  wire \zhuangtai_0_2/SRINVNOT ;  wire \zhuangtai_0_2/CLKINVNOT ;  wire \zhuangtai_1_1/DXMUX ;  wire \zhuangtai_1_1/REVUSED ;  wire \zhuangtai_1_1/SRINVNOT ;  wire \zhuangtai_1_1/CLKINVNOT ;  wire \count<4>/ENABLE ;  wire \count<4>/O ;  wire \sdata/ENABLE ;  wire \sdata/O ;  wire \datain<0>/ENABLE ;  wire \datain<0>/O ;  wire \rst/INBUF ;  wire \datain<1>/ENABLE ;  wire \datain<1>/O ;  wire \datain<2>/ENABLE ;  wire \datain<2>/O ;  wire \datain<3>/ENABLE ;  wire \datain<3>/O ;  wire \sclk_BUFGP/BUFG/S_INVNOT ;  wire \count_2/DXMUX ;  wire \_n0001<2>2/O ;  wire \_n0001<2>1/O_pack_1 ;  wire \count_2/SRINVNOT ;  wire \count_2/CLKINVNOT ;  wire CHOICE732;  wire \_n0008_SW3/O_pack_1 ;  wire \count_1/DXMUX ;  wire \count_1/DYMUX ;  wire \_n0001<0>1/O ;  wire \count_1/SRINVNOT ;  wire \count_1/CLKINVNOT ;  wire \count_3/DXMUX ;  wire \_n0001<3>/O ;  wire \_n0001<3>_SW2/O_pack_1 ;  wire \count_3/SRINVNOT ;  wire \count_3/CLKINVNOT ;  wire \count_4/DXMUX ;  wire \_n0001<4>/O ;  wire \_n0001<4>_SW1/O_pack_1 ;  wire \count_4/SRINVNOT ;  wire \count_4/CLKINVNOT ;  wire \_n0002<13>211_SW0/O_pack_1 ;  wire \datain_13/REVUSED ;  wire \datain_13/DYMUX ;  wire \_n0002<13>211/O ;  wire \datain_13/SRINVNOT ;  wire \datain_13/CLKINVNOT ;  wire \datain_10/DXMUX ;  wire \_n0002<10>1/O ;  wire \_n0002<10>1_SW0/O_pack_1 ;  wire \datain_10/SRINVNOT ;  wire \datain_10/CLKINVNOT ;  wire N11;  wire \Ker111_SW0/O_pack_1 ;  wire \datain_11/DXMUX ;  wire \_n0002<11>1/O ;  wire \_n0002<11>1_SW0/O_pack_1 ;  wire \datain_11/SRINVNOT ;  wire \datain_11/CLKINVNOT ;  wire N26;  wire \datain_12/REVUSED ;  wire \datain_12/DYMUX ;  wire \_n0002<12>161/O ;  wire \datain_12/SRINVNOT ;  wire \datain_12/CLKINVNOT ;  wire \datain_14/DXMUX ;  wire \_n0002<14>1/O ;  wire \_n0002<14>1_SW0/O_pack_1 ;  wire \datain_14/SRINVNOT ;  wire \datain_14/CLKINVNOT ;  wire N71;  wire \_n0001<4>_SW0_SW1/O_pack_1 ;  wire VCC;  wire GND;  wire [0 : 0] _n0003;  wire [1 : 1] _n0001;  initial $sdf_annotate("shuju_timesim.sdf");  X_OPAD \datain<4>/PAD  (    .PAD(datain[4])  );  X_TRI datain_4_OBUF (    .I(\datain<4>/O ),    .CTL(\datain<4>/ENABLE ),    .O(datain[4])  );  X_INV \datain<4>/ENABLEINV  (    .I(GTS),    .O(\datain<4>/ENABLE )  );  X_OPAD \datain<5>/PAD  (    .PAD(datain[5])  );  X_TRI datain_5_OBUF (    .I(\datain<5>/O ),    .CTL(\datain<5>/ENABLE ),    .O(datain[5])  );  X_INV \datain<5>/ENABLEINV  (    .I(GTS),    .O(\datain<5>/ENABLE )  );  X_OPAD \datain<6>/PAD  (    .PAD(datain[6])  );  X_TRI datain_6_OBUF (    .I(\datain<6>/O ),    .CTL(\datain<6>/ENABLE ),    .O(datain[6])  );  X_INV \datain<6>/ENABLEINV  (    .I(GTS),    .O(\datain<6>/ENABLE )  );  X_OPAD \datain<7>/PAD  (    .PAD(datain[7])  );  X_TRI datain_7_OBUF (    .I(\datain<7>/O ),    .CTL(\datain<7>/ENABLE ),    .O(datain[7])  );  X_INV \datain<7>/ENABLEINV  (    .I(GTS),    .O(\datain<7>/ENABLE )  );  X_OPAD \datain<8>/PAD  (    .PAD(datain[8])  );  X_TRI datain_8_OBUF (    .I(\datain<8>/O ),    .CTL(\datain<8>/ENABLE ),    .O(datain[8])  );  X_INV \datain<8>/ENABLEINV  (    .I(GTS),    .O(\datain<8>/ENABLE )  );  X_OPAD \datain<9>/PAD  (    .PAD(datain[9])  );  X_TRI datain_9_OBUF (    .I(\datain<9>/O ),    .CTL(\datain<9>/ENABLE ),    .O(datain[9])  );  X_INV \datain<9>/ENABLEINV  (    .I(GTS),    .O(\datain<9>/ENABLE )  );  X_OPAD \datain<10>/PAD  (    .PAD(datain[10])  );  X_TRI datain_10_OBUF (    .I(\datain<10>/O ),    .CTL(\datain<10>/ENABLE ),    .O(datain[10])  );  X_INV \datain<10>/ENABLEINV  (    .I(GTS),    .O(\datain<10>/ENABLE )  );  X_IPAD \sclk/PAD  (    .PAD(sclk)  );  X_BUF \sclk_BUFGP/IBUFG_0  (    .I(sclk),    .O(\sclk/INBUF )  );  X_BUF \sclk/IFF/IMUX  (    .I(\sclk/INBUF ),    .O(\sclk_BUFGP/IBUFG )  );  X_OPAD \datain<11>/PAD  (    .PAD(datain[11])  );  X_TRI datain_11_OBUF (    .I(\datain<11>/O ),    .CTL(\datain<11>/ENABLE ),    .O(datain[11])  );  X_INV \datain<11>/ENABLEINV  (    .I(GTS),    .O(\datain<11>/ENABLE )  );  X_OPAD \datain<12>/PAD  (    .PAD(datain[12])  );  X_TRI datain_12_OBUF (    .I(\datain<12>/O ),    .CTL(\datain<12>/ENABLE ),    .O(datain[12])  );  X_INV \datain<12>/ENABLEINV  (    .I(GTS),    .O(\datain<12>/ENABLE )  );  X_OPAD \zhuangtai<0>/PAD  (    .PAD(zhuangtai[0])  );  X_TRI zhuangtai_0_OBUF (    .I(\zhuangtai<0>/O ),    .CTL(\zhuangtai<0>/ENABLE ),    .O(zhuangtai[0])  );  X_INV \zhuangtai<0>/ENABLEINV  (    .I(GTS),    .O(\zhuangtai<0>/ENABLE )  );  X_OPAD \datain<13>/PAD  (    .PAD(datain[13])  );  X_TRI datain_13_OBUF (    .I(\datain<13>/O ),    .CTL(\datain<13>/ENABLE ),    .O(datain[13])  );  X_INV \datain<13>/ENABLEINV  (    .I(GTS),    .O(\datain<13>/ENABLE )  );  X_OPAD \zhuangtai<1>/PAD  (    .PAD(zhuangtai[1])  );  X_TRI zhuangtai_1_OBUF (    .I(\zhuangtai<1>/O ),    .CTL(\zhuangtai<1>/ENABLE ),    .O(zhuangtai[1])  );  X_INV \zhuangtai<1>/ENABLEINV  (    .I(GTS),    .O(\zhuangtai<1>/ENABLE )  );  X_OPAD \datain<14>/PAD  (    .PAD(datain[14])  );  X_TRI datain_14_OBUF (    .I(\datain<14>/O ),    .CTL(\datain<14>/ENABLE ),    .O(datain[14])  );  X_INV \datain<14>/ENABLEINV  (    .I(GTS),    .O(\datain<14>/ENABLE )  );  X_OPAD \zhuangtai<2>/PAD  (    .PAD(zhuangtai[2])  );  X_TRI zhuangtai_2_OBUF (    .I(\zhuangtai<2>/O ),    .CTL(\zhuangtai<2>/ENABLE ),    .O(zhuangtai[2])  );  X_INV \zhuangtai<2>/ENABLEINV  (    .I(GTS),    .O(\zhuangtai<2>/ENABLE )  );  X_OPAD \datain<15>/PAD  (    .PAD(datain[15])  );  X_TRI datain_15_OBUF (    .I(\datain<15>/O ),    .CTL(\datain<15>/ENABLE ),    .O(datain[15])  );  X_INV \datain<15>/ENABLEINV  (    .I(GTS),    .O(\datain<15>/ENABLE )  );  X_OPAD \zhuangtai<3>/PAD  (    .PAD(zhuangtai[3])  );  X_TRI zhuangtai_3_OBUF (    .I(\zhuangtai<3>/O ),    .CTL(\zhuangtai<3>/ENABLE ),    .O(zhuangtai[3])  );  X_INV \zhuangtai<3>/ENABLEINV  (    .I(GTS),    .O(\zhuangtai<3>/ENABLE )  );  X_OPAD \zhuangtai<4>/PAD  (    .PAD(zhuangtai[4])  );  X_TRI zhuangtai_4_OBUF (    .I(\zhuangtai<4>/O ),    .CTL(\zhuangtai<4>/ENABLE ),    .O(zhuangtai[4])  );  X_INV \zhuangtai<4>/ENABLEINV  (    .I(GTS),    .O(\zhuangtai<4>/ENABLE )  );  X_OPAD \count<0>/PAD  (    .PAD(count[0])  );  X_TRI count_0_OBUF (    .I(\count<0>/O ),    .CTL(\count<0>/ENABLE ),    .O(count[0])  );  X_INV \count<0>/ENABLEINV  (    .I(GTS),    .O(\count<0>/ENABLE )  );  X_OPAD \count<1>/PAD  (    .PAD(count[1])  );  X_TRI count_1_OBUF (    .I(\count<1>/O ),    .CTL(\count<1>/ENABLE ),    .O(count[1])  );  X_INV \count<1>/ENABLEINV  (    .I(GTS),    .O(\count<1>/ENABLE )  );  X_OPAD \count<2>/PAD  (    .PAD(count[2])  );  X_TRI count_2_OBUF (    .I(\count<2>/O ),    .CTL(\count<2>/ENABLE ),    .O(count[2])  );  X_INV \count<2>/ENABLEINV  (    .I(GTS),    .O(\count<2>/ENABLE )  );  X_OPAD \count<3>/PAD  (    .PAD(count[3])  );  X_TRI count_3_OBUF (    .I(\count<3>/O ),    .CTL(\count<3>/ENABLE ),    .O(count[3])  );  X_INV \count<3>/ENABLEINV  (    .I(GTS),    .O(\count<3>/ENABLE )  );  X_BUF \N175/XUSED  (    .I(N175),    .O(N175_0)  );  defparam _n0008_SW2.INIT = 16'h0200;  X_LUT4 _n0008_SW2 (    .ADR0(sdata_OBUF),    .ADR1(count_0),    .ADR2(count_1),    .ADR3(count_4),    .O(N175)  );  X_BUF \N197/XUSED  (    .I(N197),    .O(N197_0)  );  X_BUF \N197/YUSED  (    .I(N191),    .O(N191_0)  );  defparam _n0008_SW4.INIT = 16'hBB33;  X_LUT4 _n0008_SW4 (    .ADR0(zhuangtai_1_1),    .ADR1(datain_6),    .ADR2(VCC),    .ADR3(zhuangtai_0_1),    .O(N191)  );  X_BUF \N194/XUSED  (    .I(N194),    .O(N194_0)  );  defparam _n0008_SW7.INIT = 16'hF555;  X_LUT4 _n0008_SW7 (    .ADR0(datain_3),    .ADR1(VCC),    .ADR2(zhuangtai_1_1),    .ADR3(zhuangtai_0_1),    .O(N194)  );  X_BUF \sdata_OBUF/XUSED  (    .I(N149),    .O(N149_0)  );  X_BUF \sdata_OBUF/REVUSED_1  (    .I(CHOICE732),    .O(\sdata_OBUF/REVUSED )  );  X_BUF \sdata_OBUF/DYMUX_2  (    .I(\_n0000151/O ),    .O(\sdata_OBUF/DYMUX )  );  X_INV \sdata_OBUF/SRINV  (    .I(rst_IBUF),    .O(\sdata_OBUF/SRINVNOT )  );  X_INV \sdata_OBUF/CLKINV  (    .I(sclk_BUFGP),    .O(\sdata_OBUF/CLKINVNOT )  );  X_BUF \datain_15/DXMUX_3  (    .I(\_n0002<15>1/O ),    .O(\datain_15/DXMUX )  );  X_BUF \datain_15/YUSED  (    .I(\_n0002<15>1_SW0/O_pack_1 ),    .O(\_n0002<15>1_SW0/O )  );  X_INV \datain_15/SRINV  (    .I(rst_IBUF),    .O(\datain_15/SRINVNOT )  );  X_INV \datain_15/CLKINV  (    .I(sclk_BUFGP),    .O(\datain_15/CLKINVNOT )  );  X_BUF \CHOICE743/YUSED  (    .I(\_n0008_SW8/O_pack_1 ),    .O(\_n0008_SW8/O )  );  defparam _n0008_SW8.INIT = 16'hD5FF;  X_LUT4 _n0008_SW8 (    .ADR0(datain_3),    .ADR1(zhuangtai_0_2),    .ADR2(zhuangtai_1_1),    .ADR3(N215_0),    .O(\_n0008_SW8/O_pack_1 )  );  X_BUF \datain_5/DXMUX_4  (    .I(\_n0002<5>1/O ),    .O(\datain_5/DXMUX )  );  X_BUF \datain_5/YUSED  (    .I(\_n0002<5>1_SW0/O_pack_1 ),    .O(\_n0002<5>1_SW0/O )