module serial(clk,rst,reset,sload,sclk); //clk周期為34.92ns
  input clk,rst;
  output reset,sload,sclk;
  reg reset,sload,sclk;
  reg [7:0]sa,sb,sc,sd;
  reg [3:0]s1,s2,s3,s4,s5;

  always@(posedge clk)
    if(!rst)
	   begin
	      reset<=0;
		   sa<=0;
			s1<=0;
      end
    else
	   case(s1)
			0:if(sa==9)
				 begin
				    reset<=0;
				    s1<=1;
				 end
			  else
			    sa<=sa+1;
			1:begin
		     	  reset<=1;
			     s1<=1;
			  end
		endcase

  always@(posedge clk)
    if(!rst)
	   begin
		   sload<=1;
			sb<=0;
			sc<=0;
			s2<=0;
			s3<=0;
			s4<=0;
		end
	 else
	   case(s3)
		   0:if(sb==10)
				 begin
				    sload<=0;
					 sb<=0;
                s3<=1;
             end
           else
			    sb<=sb+1;
		   1:if(sc==2)
			    s3<=2;
           else
			    case(s2)
		          0:if(sb==159)
			           begin
				           sload<=1;
					        sb<=0;
					        s2<=1;
                    end
                  else
			           begin
				           sload<=0;
					        sb<=sb+1;
                    end
                1:if(sb==9)
			           begin
				           sload<=0;
					        sb<=0;
					        s2<=0;
							  sc<=sc+1;
                    end
                  else
			           begin
				           sload<=1;
					        sb<=sb+1;
                    end
              endcase
		   2:case(s4)
			     0:if(sb==159)
						begin
				         sload<=1;
					      s4<=1;
                  end
                else
			         begin
				         sload<=0;
					      sb<=sb+1;
                  end
				  1:begin
				       sload<=1;
						 s3<=2;
						 s4<=1;
					 end
           endcase
		endcase

  always@(posedge clk)
    if(!rst)
	   begin
		   sclk<=1;
			sd<=0;
			s5<=0;
      end
    else
	   case(s5)
	      0:if(sd==5)
		       begin
		          sclk<=1;
			       sd<=0;
					 s5<=1;
             end
           else
			    begin
				    sclk<=0;
					 sd<=sd+1;
				 end
			1:if(sd==4)
		       begin
		          sclk<=0;
			       sd<=1;
					 s5<=0;
             end
           else
				 sd<=sd+1;
		endcase

  
endmodule