?? data.v
字號:
module data(sclk,sdata);
input sclk;
output sdata;
reg sdata;
reg [4:0]e,state6;
reg [15:0]datain;
initial
begin
sdata<=0;
e<=0;
datain<=16'b0000000100000000; //configuration
state6<=0;
end
always@(negedge sclk)
begin
case(state6)
0:if(e==16)
begin
datain<=16'b0001000110010000; //PGA gain:400(12dB)
e<=0;
state6<=1;
end
else
begin
datain<=(datain<<1);
sdata<=datain[15];
e<=e+1;
end
1:if(e==16)
begin
datain<=16'b0010000000001000; //OB clamp level:32LSB
e<=0;
state6<=2;
end
else
begin
datain<=(datain<<1);
sdata<=datain[15];
e<=e+1;
end
2:if(e==16)
sdata<=0;
else
begin
datain<=(datain<<1);
sdata<=datain[15];
e<=e+1;
end
endcase
end
endmodule
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