?? icx229.syr
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Release 7.1.04i - xst H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 2.78 s | Elapsed : 0.00 / 2.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 2.78 s | Elapsed : 0.00 / 2.00 s --> Reading design: ICX229.prjTABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : "ICX229.prj"Input Format : mixedIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : "ICX229"Output Format : NGCTarget Device : xc3s400-4-pq208---- Source OptionsTop Module Name : ICX229Automatic FSM Extraction : YESFSM Encoding Algorithm : AutoFSM Style : lutRAM Extraction : YesRAM Style : AutoROM Extraction : YesROM Style : AutoMux Extraction : YESMux Style : AutoDecoder Extraction : YESPriority Encoder Extraction : YESShift Register Extraction : YESLogical Shifter Extraction : YESXOR Collapsing : YESResource Sharing : YESMultiplier Style : autoAutomatic Register Balancing : No---- Target OptionsAdd IO Buffers : YESGlobal Maximum Fanout : 500Add Generic Clock Buffer(BUFG) : 8Register Duplication : YESEquivalent register Removal : YESSlice Packing : YESPack IO Registers into IOBs : auto---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Keep Hierarchy : NOGlobal Optimization : AllClockNetsRTL Output : YesWrite Timing Constraints : NOHierarchy Separator : /Bus Delimiter : <>Case Specifier : maintainSlice Utilization Ratio : 100Slice Utilization Ratio Delta : 5---- Other Optionslso : ICX229.lsoRead Cores : YEScross_clock_analysis : NOverilog2001 : YESsafe_implementation : NoOptimize Instantiated Primitives : NOuse_clock_enable : Yesuse_sync_set : Yesuse_sync_reset : Yesenable_auto_floorplanning : No==================================================================================================================================================* HDL Compilation *=========================================================================Compiling verilog file "ICX229.v"Module <ICX229> compiledNo errors in compilationAnalysis of file <"ICX229.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <ICX229>.Module <ICX229> is correct for synthesis. Set property "resynthesize = true" for unit <ICX229>.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <ICX229>. Related source file is "ICX229.v".INFO:Xst:2117 - HDL ADVISOR - Mux Selector <state1> of Case statement line 108 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can: - add an 'init' attribute on signal <state1> (optimization is then done without any risk) - use the attribute 'signal_encoding user' to avoid onehot optimization - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization Found finite state machine <FSM_0> for signal <state>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 5 | | Outputs | 3 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_1> for signal <state0>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 4 | | Inputs | 0 | | Outputs | 4 | | Clock | clk (rising_edge) | | Clock enable | $n0008 (positive) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_2> for signal <state1>. ----------------------------------------------------------------------- | States | 8 | | Transitions | 8 | | Inputs | 0 | | Outputs | 10 | | Clock | clk (rising_edge) | | Clock enable | $n0012 (positive) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_3> for signal <state2>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 4 | | Inputs | 0 | | Outputs | 4 | | Clock | clk (rising_edge) | | Clock enable | $n0021 (positive) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_4> for signal <state3>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 6 | | Inputs | 3 | | Outputs | 3 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_5> for signal <state4>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 58 | | Inputs | 15 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_6> for signal <state5>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 12 | | Inputs | 7 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_7> for signal <state7>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 37 | | Inputs | 11 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_8> for signal <state8>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 5 | | Outputs | 3 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_9> for signal <state10>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 27 | | Inputs | 10 | | Outputs | 3 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT |?? 快捷鍵說明
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