?? icx229.syr
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----------------------------------------------------------------------- Found finite state machine <FSM_10> for signal <state11>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 5 | | Outputs | 3 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_11> for signal <state13>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 43 | | Inputs | 14 | | Outputs | 4 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_12> for signal <state14>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 12 | | Inputs | 8 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_13> for signal <state16>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 10 | | Inputs | 4 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_14> for signal <state17>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 10 | | Inputs | 4 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_15> for signal <state18>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 10 | | Inputs | 4 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | synchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <h1>. Found 1-bit register for signal <h2>. Found 1-bit register for signal <sub>. Found 1-bit register for signal <r>. Found 1-bit register for signal <v1>. Found 1-bit register for signal <v2>. Found 1-bit register for signal <v3>. Found 1-bit register for signal <v4>. Found 1-bit register for signal <v1h>. Found 1-bit register for signal <v3h>. Found 15-bit adder for signal <$n0152> created at line 68. Found 3-bit adder for signal <$n0153> created at line 199. Found 15-bit adder for signal <$n0154> created at line 245. Found 15-bit adder for signal <$n0155> created at line 245. Found 15-bit adder for signal <$n0156> created at line 443. Found 15-bit adder for signal <$n0157> created at line 443. Found 15-bit adder for signal <$n0158> created at line 566. Found 15-bit adder for signal <$n0159> created at line 566. Found 15-bit adder for signal <$n0160> created at line 673. Found 15-bit adder for signal <$n0161> created at line 673. Found 31-bit adder for signal <$n0162> created at line 825. Found 31-bit adder for signal <$n0163> created at line 875. Found 31-bit adder for signal <$n0164> created at line 925. Found 15-bit adder for signal <$n0165>. Found 15-bit register for signal <a>. Found 15-bit register for signal <b>. Found 15-bit register for signal <d>. Found 15-bit register for signal <e>. Found 15-bit register for signal <g>. Found 15-bit register for signal <h>. Found 15-bit register for signal <i>. Found 15-bit register for signal <j>. Found 15-bit register for signal <l>. Found 15-bit register for signal <m>. Found 31-bit register for signal <o>. Found 31-bit register for signal <p>. Found 31-bit register for signal <q>. Found 3-bit register for signal <s>. Summary: inferred 16 Finite State Machine(s). inferred 256 D-type flip-flop(s). inferred 14 Adder/Subtractor(s).Unit <ICX229> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Analyzing FSM <FSM_15> for best encoding.Optimizing FSM <FSM_15> on signal <state18[1:5]> with speed1 encoding.------------------- State | Encoding------------------- 000 | 10000 001 | 01000 010 | 00100 011 | 00010 100 | 00001-------------------Analyzing FSM <FSM_14> for best encoding.Optimizing FSM <FSM_14> on signal <state17[1:5]> with speed1 encoding.------------------- State | Encoding------------------- 000 | 10000 001 | 01000 010 | 00100 011 | 00010 100 | 00001-------------------Analyzing FSM <FSM_13> for best encoding.Optimizing FSM <FSM_13> on signal <state16[1:5]> with speed1 encoding.------------------- State | Encoding------------------- 000 | 10000 001 | 01000 010 | 00100 011 | 00010 100 | 00001-------------------Analyzing FSM <FSM_12> for best encoding.Optimizing FSM <FSM_12> on signal <state14[1:5]> with speed1 encoding.------------------- State | Encoding------------------- 000 | 10000 001 | 01000 010 | 00100 011 | 00010 100 | 00001-------------------Analyzing FSM <FSM_11> for best encoding.Optimizing FSM <FSM_11> on signal <state13[1:2]> with sequential encoding.------------------- State | Encoding------------------- 000 | 00 001 | 01 010 | 10 011 | 11-------------------Analyzing FSM <FSM_10> for best encoding.Optimizing FSM <FSM_10> on signal <state11[1:2]> with sequential encoding.------------------- State | Encoding------------------- 000 | 00 001 | 01 010 | 10-------------------Analyzing FSM <FSM_9> for best encoding.Optimizing FSM <FSM_9> on signal <state10[1:2]> with sequential encoding.------------------- State | Encoding------------------- 000 | 00 001 | 01 010 | 10-------------------Analyzing FSM <FSM_8> for best encoding.Optimizing FSM <FSM_8> on signal <state8[1:2]> with sequential encoding.------------------- State | Encoding------------------- 000 | 00 001 | 01 010 | 10-------------------Analyzing FSM <FSM_7> for best encoding.Optimizing FSM <FSM_7> on signal <state7[1:5]> with speed1 encoding.------------------- State | Encoding------------------- 000 | 10000 001 | 01000 010 | 00100 011 | 00010 100 | 00001-------------------Analyzing FSM <FSM_6> for best encoding.Optimizing FSM <FSM_6> on signal <state5[1:5]> with speed1 encoding.------------------- State | Encoding------------------- 000 | 10000 001 | 01000 010 | 00100 011 | 00010 100 | 00001-------------------Analyzing FSM <FSM_5> for best encoding.Optimizing FSM <FSM_5> on signal <state4[1:5]> with speed1 encoding.------------------- State | Encoding------------------- 000 | 10000 001 | 01000 010 | 00100 011 | 00010 100 | 00001-------------------Analyzing FSM <FSM_4> for best encoding.Optimizing FSM <FSM_4> on signal <state3[1:2]> with sequential encoding.------------------- State | Encoding------------------- 000 | 00?? 快捷鍵說明
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