?? cnt60.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY cnt60 is
port(clk,rst : in std_logic;
co : out std_logic;
qout : out std_logic_vector(7 downto 0));
END cnt60;
architecture behave of cnt60 is
signal qh,ql : std_logic_vector(3 downto 0);
BEGIN
process(rst,clk)
begin
if (rst='0') then ql<="0000"; qh<="0000"; co<='0';
elsif (clk'event and clk='1') then
if (ql=9) then ql<="0000";
if (qh=5) then qh<="0000";co<='1';
else qh<=qh+1;co<='0';
end if;
else ql<=ql+1;
end if;
end if;
qout<=qh&ql;
end process;
END behave;
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