-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- Revision Control Information
--
-- Description	:  
--
-- Copyright 2003 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;


ENTITY ber_threshold IS
	GENERIC
	(
		BER_threshold_val : NATURAL := 125;
		BER_monitor_len : NATURAL := 500;
		monitor_len_max : NATURAL := 10;
		numerr_max : NATURAL := 10
		
	);
	PORT
	(
		clk : in std_logic;
		reset : in std_logic;
		numerr : in std_logic_vector ( numerr_max downto 1);
		source_val : in std_logic;
		source_sop : in std_logic;
		source_eop : in std_logic;
       	out_sync : out std_logic 
	);
END ber_threshold;


ARCHITECTURE arch_ber_threshold OF ber_threshold IS
	SIGNAL count_bits : STD_LOGIC_VECTOR(monitor_len_max-1 downto 0);
	SIGNAL flag_out_sync : STD_LOGIC;
	SIGNAL numerr_cnt : STD_LOGIC_VECTOR(numerr_max-1 downto 0);
	SIGNAL numerr_base : STD_LOGIC_VECTOR(numerr_max-1 downto 0);
	
	-- initial - reset state, design assumes system is in sync
	-- monitor_BER - monitor bit error rate by counting number of errors 
	--			     based on numerr, in the frame of size monitor_len_max.
	-- reach_EOF - reached end of frame (EOF).  Keep track of length of frame 
	--			   being monitor by counting valid output bits, source_val.
	-- error_OL - number of errors detected is over of limit (OL).
	TYPE sync_sm IS (initial, monitor_BER, reach_EOF, error_OL, halt); 
	SIGNAL sync_state : sync_sm;
	
	SIGNAL out_sync_sig : STD_LOGIC;
	SIGNAL source_sop_del : STD_LOGIC_VECTOR(2 downto 0);
	
BEGIN
	out_sync <= out_sync_sig;
	
	PROCESS (clk, reset)
	BEGIN
		IF reset = '1' THEN
		    count_bits <= (others => '0');
		ELSIF rising_edge(clk) THEN
			IF (sync_state = reach_EOF OR sync_state = error_OL) THEN
				count_bits <= (others => '0');
			ELSIF (source_val = '1' AND sync_state = monitor_BER) THEN
				count_bits <= count_bits + 1;
			END IF;
		END IF;
	END PROCESS;
	
	PROCESS (clk, reset)
	BEGIN
		IF reset = '1' THEN
		    source_sop_del <= (others => '0');
		ELSIF rising_edge(clk) THEN
			source_sop_del(2) <= source_sop;
			source_sop_del(1) <= source_sop_del(2);
			source_sop_del(0) <= source_sop_del(1);
		END IF;
	END PROCESS;
	
	
	PROCESS (clk, reset)
	BEGIN
	    IF reset = '1' THEN
			numerr_base <= (others => '0');
	    ELSIF rising_edge(clk) THEN
			IF (source_sop_del(0) = '1') THEN
				numerr_base <= (others => '0');
			ELSIF (sync_state = reach_EOF) THEN
			    numerr_base <= numerr;
			END IF;
		END IF;
	END PROCESS;
	
	PROCESS (clk, reset)
	BEGIN
	    IF reset = '1' THEN
	        numerr_cnt <= (others => '0');
	    ELSIF rising_edge(clk) THEN
	        IF (sync_state = reach_EOF OR sync_state = error_OL OR sync_state = halt)  THEN
			    numerr_cnt <= (others => '0');
			ELSE
			    numerr_cnt <= numerr - numerr_base;
		    END IF;
		END IF;
	END PROCESS;
	
		
	PROCESS (clk, reset)
	BEGIN
	    IF reset = '1' THEN
	        out_sync_sig <= '0';
	    ELSIF rising_edge(clk) THEN
	 		CASE sync_state IS
				WHEN initial =>
					out_sync_sig <= '0';
				WHEN monitor_BER =>
					out_sync_sig <= '0';
				WHEN reach_EOF =>
					out_sync_sig <= '0';
				WHEN error_OL =>
					out_sync_sig <= '1';
				WHEN halt =>
					out_sync_sig <= '0';
			END CASE;
		END IF;
	END PROCESS;
	
	PROCESS (clk, reset)
	BEGIN
		IF reset = '1' THEN
			sync_state <= initial;
		ELSIF rising_edge(clk) THEN
			IF (sync_state = error_OL) THEN
				sync_state <= halt;
			ELSIF (numerr_cnt >= BER_threshold_val)  THEN
				sync_state <= error_OL;
			ELSIF (count_bits >= BER_monitor_len or source_eop = '1') THEN
				sync_state <= reach_EOF;
			ELSIF ( (sync_state = halt AND source_sop = '1') OR (sync_state = reach_EOF OR sync_state = monitor_BER or sync_state = initial) ) THEN
				sync_state <= monitor_BER;
			END IF;
		END IF;
	END PROCESS;
				
	
END arch_ber_threshold;