module re_stbc(redata_i1,redata_i2,redata_q1,redata_q2,dataout_i,dataout_q,clk,enable);
output [2:0] dataout_i,dataout_q;
reg [2:0] dataout_i,dataout_q;
input [3:0] redata_i1,redata_i2,redata_q1,redata_q2;
input enable,clk;
reg [3:0] ram1_i1,ram1_i2,ram1_q1,ram1_q2,ram2_i1,ram2_i2,ram2_q1,ram2_q2;
reg [3:0] ram3_i1,ram3_i2,ram3_q1,ram3_q2,ram4_i1,ram4_i2,ram4_q1,ram4_q2;
reg [5:0] rechannel_i1,rechannel_i2,rechannel_q1,rechannel_q2;
reg clk_3;
//reg [2:0] h11_i,h12_i,h21_i,h22_i,h11_q,h12_q,h21_q,h22_q;
initial 
begin
//sum=h11_i*h11_i+h11_q*h11_q+h12_i*h12_i+h12_q*h12_q+h21_i*h21_i+h21_q*h21_q+h22_i*h22_i+h22_q*h22_q;
clk_3<=0;
end
always @ (posedge clk)begin
if(enable)begin
ram1_i1<=redata_i1;
ram1_i2<=redata_i2;
ram1_q1<=redata_q1;
ram1_q2<=redata_q2;
ram2_i1<=ram1_i1; 
ram2_i2<=ram1_i2;
ram2_q1<=ram1_q1;
ram2_q2<=ram1_q2;
clk_3<=~clk_3;
if(clk_3==0)begin
dataout_i<=rechannel_i1[5:2];
dataout_q<=rechannel_q1[5:2];

end
else
begin
dataout_i<=rechannel_i2[5:2];
dataout_q<=rechannel_q2[5:2];
ram3_i1<=ram1_i1;
ram3_i2<=ram1_i2;
ram3_q1<=ram1_q1;
ram3_q2<=ram1_q2;
ram4_i1<=ram2_i1;
ram4_i2<=ram2_i2;
ram4_q1<=ram2_q1;
ram4_q2<=ram2_q2;
rechannel_i1<=ram3_i1+ram3_i2+ram4_i1+ram4_i2;
rechannel_q1<=ram3_q1-ram3_q2+ram4_q1-ram4_q2;
rechannel_i2<=ram3_i1-ram3_i2+ram4_i1-ram4_i2;
rechannel_q2<=ram3_q1+ram3_q2+ram4_q1+ram4_q2;
end
end
end

endmodule