module pestbc(data,datain_i,datain_q,clk_user,enable);
output [2:0] datain_i,datain_q;
output enable;
reg [2:0] datain_i,datain_q;
reg enable;
input data;
input clk_user;
reg [5:0] shifter;
integer count=0;
initial
begin
shifter<=0;
datain_i<=0;
datain_q<=0;
count<=0;
enable<=0;
end
always @ (posedge clk_user)begin
shifter[0]<=data;
shifter[1]<=shifter[0];
shifter[2]<=shifter[1];
shifter[3]<=shifter[2];
shifter[4]<=shifter[3];
shifter[5]<=shifter[4];
count<=count+1;
if(count==5)begin
datain_i<=shifter[5:3];
datain_q<=shifter[2:0];
enable<=1;
count<=0;
end
else if(count==0)enable<=0;
end
endmodule