module simple_channel(dataout_i1,dataout_q1,dataout_i2,dataout_q2,redata_i1,redata_i2,redata_q1,redata_q2,clk);
input [2:0] dataout_i1,dataout_q1,dataout_i2,dataout_q2;
input clk;
output [3:0] redata_i1,redata_i2,redata_q1,redata_q2;
reg [3:0] redata_i1,redata_i2,redata_q1,redata_q2;
always @ (posedge clk)begin
redata_i1<=rece(dataout_i1,dataout_i2);
redata_i2<=rece(dataout_i1,dataout_i2);
redata_q1<=rece(dataout_q1,dataout_q2);
redata_q2<=rece(dataout_q1,dataout_q2);

end

function [3:0] rece;
input [2:0] data1,data2;                             
begin         
if(data1[2]^data2[2]==0)
rece=data1+data2;
else if(data1[2]==0&&(data1[1:0]>=data2[1:0]))begin
rece[3:2]=2`b00;
rece[1:0]=data1[1:0]-data2[1:0];
end
else if(data1[2]==0&&data1[1:0]<data2[1:0])begin
rece[3:2]=2`b00;
rece[1:0]=data2[1:0]-data1[1:0];
end
else if(data2[2]==0&&data2[1:0]>=data1[1:0])begin
rece[3:2]=2`b00;
rece[1:0]=data2[1:0]-data1[1:0];
end
else if(data2[2]==0&&data2[1:0]<data1[1:0])
begin
rece[3:2]=2`b10;
rece[1:0]=data1[1:0]-data2[1:0];
end
end
endfunction
endmodule