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</style></HEAD><BODY align="left" style='background-color: #ffffff;'><DIV align="left"><TABLE width="95%" border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - FFT MegaCore Function v7.1</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width="60%"><TR><TD><B>Entity Name</B></TD><TD>auk_dspip_r22sdf_top_fft_71</TD></TR><TR><TD><B>Variation Name</B></TD><TD>fft</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>VHDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>C:\MyDesigns\LTE_ofdm_kernel\source\fft71</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>The MegaWizard interface is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width="100%"><TR align="left"><TH align="left" align="top" width="25%"><B>File</B></TH><TH align="left"><B>Description</B></TH></TR><TR><TD>fft.vhd</TD><TD>A MegaCore<small><sup>®</sup></small> function variation file, which defines a VHDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>fft.cmp</TD><TD>A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>fft.bsf</TD><TD>Quartus<small><sup>®</sup></small> II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.</TD></TR><TR><TD>fft.vho</TD><TD>VHDL IP Functional Simulation model.</TD></TR><TR><TD>fft_tb.vhd</TD><TD>VHDL Testbench</TD></TR><TR><TD>fft_model.m</TD><TD>Matlab m-file describing a Matlab bit-accurate model.</TD></TR><TR><TD>fft_tb.m</TD><TD>Matlab Testbench</TD></TR><TR><TD>fft_nativelink.tcl</TD><TD>A Tcl script to setup NativeLink in the Quartus II software.</TD></TR><TR><TD>real_input.txt</TD><TD>Text file containing input real component random data. This file is read by the generated VHDL or Verilog HDL and Matlab testbenches.</TD></TR><TR><TD>imag_input.txt</TD><TD>Text file containing input imaginary component random data. This file is read by the generated VHDL or Verilog HDL and Matlab testbenches.</TD></TR><TR><TD>fft_fft.fsi</TD><TD>A fsi file describing the FFT. This file is used for fast simulation in DSP Builder.</TD></TR><TR><TD>fft_bit_reverse_top.vhd</TD><TD>Example VHDL top level with bit reversal module.</TD></TR><TR><TD>fft_opt_twr1.hex</TD><TD>Intel Hex-format ROM initialization file.</TD></TR><TR><TD>fft_opt_twi1.hex</TD><TD>Intel Hex-format ROM initialization file.</TD></TR><TR><TD>fft_opt_twr2.hex</TD><TD>Intel Hex-format ROM initialization file.</TD></TR><TR><TD>fft_opt_twi2.hex</TD><TD>Intel Hex-format ROM initialization file.</TD></TR><TR><TD>fft_opt_twr3.hex</TD><TD>Intel Hex-format ROM initialization file.</TD></TR><TR><TD>fft_opt_twi3.hex</TD><TD>Intel Hex-format ROM initialization file.</TD></TR><TR><TD>fft_opt_twr4.hex</TD><TD>Intel Hex-format ROM initialization file.</TD></TR><TR><TD>fft_opt_twi4.hex</TD><TD>Intel Hex-format ROM initialization file.</TD></TR><TR><TD>fft_opt_twr5.hex</TD><TD>Intel Hex-format ROM initialization file.</TD></TR><TR><TD>fft_opt_twi5.hex</TD><TD>Intel Hex-format ROM initialization file.</TD></TR><TR><TD>fft.html</TD><TD>The MegaCore function report file.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width="75%"><TR align="left"><TH align="left"><B>Name</B></TH><TH align="left"><B>Direction</B></TH><TH align="left"><B>Width</B></TH></TR><TR><TD>clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reset_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>fftpts_in</TD><TD>INPUT</TD><TD>12</TD></TR><TR><TD>fftpts_out</TD><TD>OUTPUT</TD><TD>12</TD></TR><TR><TD>inverse</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sink_valid</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sink_sop</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sink_eop</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sink_real</TD><TD>INPUT</TD><TD>16</TD></TR><TR><TD>sink_imag</TD><TD>INPUT</TD><TD>16</TD></TR><TR><TD>sink_ready</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>sink_error</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>source_error</TD><TD>OUTPUT</TD><TD>2</TD></TR><TR><TD>source_ready</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>source_sop</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>source_eop</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>source_valid</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>source_real</TD><TD>OUTPUT</TD><TD>31</TD></TR><TR><TD>source_imag</TD><TD>OUTPUT</TD><TD>31</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>?? 快捷鍵說明
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