# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		A8259_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY APEX20KE
set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY A8259
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:44:15  AUGUST 31, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name VHDL_FILE CWRD_REG.VHD
set_global_assignment -name VHDL_FILE INITCNTL.VHD
set_global_assignment -name VHDL_FILE INT_LTCH.VHD
set_global_assignment -name VHDL_FILE INT_SEQ.VHD
set_global_assignment -name VHDL_FILE IR_REG.VHD
set_global_assignment -name VHDL_FILE IS_REG.VHD
set_global_assignment -name VHDL_FILE OCW2_REG.VHD
set_global_assignment -name VHDL_FILE OCW3_REG.VHD
set_global_assignment -name VHDL_FILE OCW_DCDE.VHD
set_global_assignment -name VHDL_FILE PRI_RES.VHD
set_global_assignment -name VHDL_FILE RD_MUX.VHD
set_global_assignment -name VHDL_FILE RW_CNTL.VHD
set_global_assignment -name VHDL_FILE SEQ_CNTL.VHD
set_global_assignment -name VHDL_FILE VECT_MUX.VHD
set_global_assignment -name VHDL_FILE A8259.vhd
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
set_global_assignment -name MAX_SCC_SIZE 50
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX NORMAL
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<NONE>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
set_global_assignment -name EDA_SIMULATION_TOOL "<NONE>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING ON
set_global_assignment -name DRC_REPORT_TOP_FANOUT ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZE_TIMING NORMAL_COMPILATION
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE EPC2
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name EXCALIBUR_CONFIGURATION_DEVICE EPC2
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC2
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE EPC1
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE EPC2
set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPC2