-- Xilinx Vhdl produced by program ngd2vhdl C.16
-- Command: -w dec_vit.nga time_sim.vhd 
-- Options: -w -ti UUT 
-- Date: Fri Sep 01 10:10:15 2000 
-- Input file: dec_vit.nga
-- Output file: time_sim.vhd
-- Tmp file: C:/TEMP/xil_4
-- Design name: decoder_vit
-- Xilinx: C:/Fndtn
-- # of Entities: 1
-- Device: v300bg352-5

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

-- Model for  TOC (Tristate-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity TOC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 0 ns);
  port(O : out std_ulogic := '0');
  attribute VITAL_LEVEL0 of TOC : entity is TRUE;
end TOC;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    O <= '1';
    if (WIDTH <= 0 ns) then
       O <= '0';
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end TOC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity DECODER_VIT is 
  port (
    CLK_EN : in STD_LOGIC := 'X'; 
    CLK : in STD_LOGIC := 'X'; 
    WRMEM : out STD_LOGIC; 
    VALID_OUT : out STD_LOGIC; 
    BIT_OUT : out STD_LOGIC; 
    LOAD_READY : out STD_LOGIC; 
    LOAD_DATA : in STD_LOGIC := 'X'; 
    RESET : in STD_LOGIC := 'X'; 
    DATATOMEM : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    DATATODEC : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    BIT_IN : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    ADDR : out STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end DECODER_VIT;

architecture STRUCTURE of DECODER_VIT is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  component TOC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 0 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal N_CLK_EN : STD_LOGIC; 
  signal C1671_IBUFG : STD_LOGIC; 
  signal N_WRMEM : STD_LOGIC; 
  signal N_VALID_OUT : STD_LOGIC; 
  signal N_BIT_OUT : STD_LOGIC; 
  signal N_LOAD_READY : STD_LOGIC; 
  signal N_LOAD_DATA : STD_LOGIC; 
  signal N_RESET : STD_LOGIC; 
  signal CLK_BUFGPED : STD_LOGIC; 
  signal U2_N2035 : STD_LOGIC; 
  signal U2_N2036 : STD_LOGIC; 
  signal U6_N258 : STD_LOGIC; 
  signal U2_N2037 : STD_LOGIC; 
  signal U2_N2043 : STD_LOGIC; 
  signal U2_N2044 : STD_LOGIC; 
  signal U2_N2045 : STD_LOGIC; 
  signal U2_N2046 : STD_LOGIC; 
  signal U2_N2047 : STD_LOGIC; 
  signal U6_N260 : STD_LOGIC; 
  signal U2_N2053 : STD_LOGIC; 
  signal U2_N2054 : STD_LOGIC; 
  signal U2_N2055 : STD_LOGIC; 
  signal U2_N2056 : STD_LOGIC; 
  signal U2_N2057 : STD_LOGIC; 
  signal U6_N263 : STD_LOGIC; 
  signal U6_N264 : STD_LOGIC; 
  signal U2_N2066 : STD_LOGIC; 
  signal U2_N2067 : STD_LOGIC; 
  signal U2_N2068 : STD_LOGIC; 
  signal U2_N2069 : STD_LOGIC; 
  signal U2_N2070 : STD_LOGIC; 
  signal U2_N2071 : STD_LOGIC; 
  signal U2_N2072 : STD_LOGIC; 
  signal U6_N267 : STD_LOGIC; 
  signal U2_N2073 : STD_LOGIC; 
  signal U6_N268 : STD_LOGIC; 
  signal U2_N2079 : STD_LOGIC; 
  signal U2_N2080 : STD_LOGIC; 
  signal U2_N2081 : STD_LOGIC; 
  signal U2_N2082 : STD_LOGIC; 
  signal U2_N2083 : STD_LOGIC; 
  signal U6_N270 : STD_LOGIC; 
  signal U2_N2085 : STD_LOGIC; 
  signal U2_N2094 : STD_LOGIC; 
  signal U2_N2006 : STD_LOGIC; 
  signal U2_N2095 : STD_LOGIC; 
  signal U2_N2007 : STD_LOGIC; 
  signal U2_N2096 : STD_LOGIC; 
  signal U2_N2008 : STD_LOGIC; 
  signal U2_N2097 : STD_LOGIC; 
  signal U2_N2009 : STD_LOGIC; 
  signal U2_N2098 : STD_LOGIC; 
  signal U2_N2010 : STD_LOGIC; 
  signal U2_N2099 : STD_LOGIC; 
  signal U2_N2011 : STD_LOGIC; 
  signal U2_N2100 : STD_LOGIC; 
  signal U2_N2012 : STD_LOGIC; 
  signal U2_N2101 : STD_LOGIC; 
  signal U2_N2013 : STD_LOGIC; 
  signal U2_N2110 : STD_LOGIC; 
  signal U2_N2111 : STD_LOGIC; 
  signal U2_N2112 : STD_LOGIC; 
  signal U2_N2113 : STD_LOGIC; 
  signal U2_N2114 : STD_LOGIC; 
  signal U2_N2115 : STD_LOGIC; 
  signal U2_N2116 : STD_LOGIC; 
  signal U2_N2117 : STD_LOGIC; 
  signal U2_N2126 : STD_LOGIC; 
  signal U2_N2127 : STD_LOGIC; 
  signal U2_N2128 : STD_LOGIC; 
  signal U2_N2129 : STD_LOGIC; 
  signal U2_N2130 : STD_LOGIC; 
  signal U2_N2131 : STD_LOGIC; 
  signal U2_N2132 : STD_LOGIC; 
  signal U2_N2133 : STD_LOGIC; 
  signal U2_N2018 : STD_LOGIC; 
  signal U2_N2019 : STD_LOGIC; 
  signal U2_N2020 : STD_LOGIC; 
  signal U2_N2021 : STD_LOGIC; 
  signal U6_N256 : STD_LOGIC; 
  signal U2_N2030 : STD_LOGIC; 
  signal U2_N2031 : STD_LOGIC; 
  signal U2_N2032 : STD_LOGIC; 
  signal U2_N2033 : STD_LOGIC; 
  signal U2_N2034 : STD_LOGIC; 
  signal U2_C291_N3 : STD_LOGIC; 
  signal SYN6062 : STD_LOGIC; 
  signal SYN6064 : STD_LOGIC; 
  signal U6_C12_N3 : STD_LOGIC; 
  signal U6_CELL19 : STD_LOGIC; 
  signal U6_C21_N3 : STD_LOGIC; 
  signal SYN6206 : STD_LOGIC; 
  signal U6_C20_N3 : STD_LOGIC; 
  signal SYN4780 : STD_LOGIC; 
  signal SYN4783 : STD_LOGIC; 
  signal SYN4656 : STD_LOGIC; 
  signal SYN15370 : STD_LOGIC; 
  signal U1_C65_C3_C3 : STD_LOGIC; 
  signal U1_C59_C3_C3 : STD_LOGIC; 
  signal SYN15322 : STD_LOGIC; 
  signal U6_C576_N16 : STD_LOGIC; 
  signal SYN4805 : STD_LOGIC; 
  signal SYN15372 : STD_LOGIC; 
  signal SYN4302 : STD_LOGIC; 
  signal SYN4335 : STD_LOGIC; 
  signal SYN15317 : STD_LOGIC; 
  signal SYN15386 : STD_LOGIC; 
  signal SYN4213 : STD_LOGIC; 
  signal SYN4882 : STD_LOGIC; 
  signal SYN4886 : STD_LOGIC; 
  signal SYN4894 : STD_LOGIC; 
  signal SYN4898 : STD_LOGIC; 
  signal SYN15327 : STD_LOGIC; 
  signal SYN15377 : STD_LOGIC; 
  signal U4_C3_N35 : STD_LOGIC; 
  signal U4_N14 : STD_LOGIC; 
  signal U4_C3_N16 : STD_LOGIC; 
  signal U4_N15 : STD_LOGIC; 
  signal U4_N16 : STD_LOGIC; 
  signal U6_C18_N29 : STD_LOGIC; 
  signal NET173 : STD_LOGIC; 
  signal U4_N17 : STD_LOGIC; 
  signal U2_C285_N3 : STD_LOGIC; 
  signal SYN4134 : STD_LOGIC; 
  signal SYN16873 : STD_LOGIC; 
  signal SYN16876 : STD_LOGIC; 
  signal SYN16877 : STD_LOGIC; 
  signal SYN16878 : STD_LOGIC; 
  signal SYN16893 : STD_LOGIC; 
  signal SYN16896 : STD_LOGIC; 
  signal SYN16897 : STD_LOGIC; 
  signal SYN16898 : STD_LOGIC; 
  signal SYN16913 : STD_LOGIC; 
  signal SYN16916 : STD_LOGIC; 
  signal SYN16917 : STD_LOGIC; 
  signal SYN16918 : STD_LOGIC; 
  signal SYN5974 : STD_LOGIC; 
  signal SYN16929 : STD_LOGIC; 
  signal SYN16931 : STD_LOGIC; 
  signal SYN16930 : STD_LOGIC; 
  signal SYN16934 : STD_LOGIC; 
  signal SYN16944 : STD_LOGIC; 
  signal SYN16946 : STD_LOGIC; 
  signal SYN16945 : STD_LOGIC; 
  signal SYN16949 : STD_LOGIC; 
  signal U2_C280_N84 : STD_LOGIC; 
  signal U2_B : STD_LOGIC; 
  signal U2_CELL6 : STD_LOGIC; 
  signal U2_C290_N3 : STD_LOGIC; 
  signal READY : STD_LOGIC; 
  signal N53 : STD_LOGIC; 
  signal SYN5309 : STD_LOGIC; 
  signal U6_C16_N3 : STD_LOGIC; 
  signal U6_C576_N9 : STD_LOGIC; 
  signal SYN5440 : STD_LOGIC; 
  signal SYN15649 : STD_LOGIC; 
  signal U2_C292_N3 : STD_LOGIC; 
  signal SYN16243 : STD_LOGIC; 
  signal U2_C292_N9 : STD_LOGIC; 
  signal SYN5576 : STD_LOGIC; 
  signal SYN5606 : STD_LOGIC; 
  signal SYN4977 : STD_LOGIC; 
  signal SYN5021 : STD_LOGIC; 
  signal SYN4941 : STD_LOGIC; 
  signal SYN4968 : STD_LOGIC; 
  signal SYN4969 : STD_LOGIC; 
  signal N54 : STD_LOGIC; 
  signal U4_C0_N35 : STD_LOGIC; 
  signal SYN4135 : STD_LOGIC; 
  signal SYN16782 : STD_LOGIC; 
  signal SYN16785 : STD_LOGIC; 
  signal SYN6141 : STD_LOGIC; 
  signal SYN16786 : STD_LOGIC; 
  signal SYN16787 : STD_LOGIC; 
  signal U4_N20 : STD_LOGIC; 
  signal SYN16802 : STD_LOGIC; 
  signal SYN16805 : STD_LOGIC; 
  signal SYN16806 : STD_LOGIC; 
  signal SYN16807 : STD_LOGIC; 
  signal U4_C0_N16 : STD_LOGIC; 
  signal SYN16820 : STD_LOGIC; 
  signal SYN16823 : STD_LOGIC; 
  signal SYN16824 : STD_LOGIC; 
  signal SYN16825 : STD_LOGIC; 
  signal U4_N21 : STD_LOGIC; 
  signal U4_N22 : STD_LOGIC; 
  signal SYN5978 : STD_LOGIC; 
  signal SYN16836 : STD_LOGIC; 
  signal SYN16838 : STD_LOGIC; 
  signal SYN16837 : STD_LOGIC; 
  signal SYN16841 : STD_LOGIC; 
  signal SYN16851 : STD_LOGIC; 
  signal SYN16853 : STD_LOGIC; 
  signal SYN16852 : STD_LOGIC; 
  signal SYN16856 : STD_LOGIC; 
  signal U4_N23 : STD_LOGIC; 
  signal U2_C282_N3 : STD_LOGIC; 
  signal SYN5277 : STD_LOGIC; 
  signal SYN5895 : STD_LOGIC; 
  signal SYN16518 : STD_LOGIC; 
  signal SYN5896 : STD_LOGIC; 
  signal SYN16521 : STD_LOGIC; 
  signal SYN5910 : STD_LOGIC; 
  signal SYN16530 : STD_LOGIC; 
  signal SYN5911 : STD_LOGIC; 
  signal SYN16533 : STD_LOGIC; 
  signal SYN16537 : STD_LOGIC; 
  signal SYN16541 : STD_LOGIC; 
  signal SYN5937 : STD_LOGIC; 
  signal SYN16549 : STD_LOGIC; 
  signal SYN5938 : STD_LOGIC; 
  signal SYN16552 : STD_LOGIC; 
  signal SYN5952 : STD_LOGIC; 
  signal SYN16560 : STD_LOGIC; 
  signal SYN5953 : STD_LOGIC; 
  signal SYN16563 : STD_LOGIC; 
  signal SYN16571 : STD_LOGIC; 
  signal SYN16567 : STD_LOGIC; 
  signal U2_C286_N3 : STD_LOGIC; 
  signal SYN16689 : STD_LOGIC; 
  signal SYN16692 : STD_LOGIC; 
  signal SYN6067 : STD_LOGIC; 
  signal SYN16693 : STD_LOGIC; 
  signal SYN16694 : STD_LOGIC; 
  signal SYN16711 : STD_LOGIC; 
  signal SYN16714 : STD_LOGIC; 
  signal SYN16715 : STD_LOGIC; 
  signal SYN16716 : STD_LOGIC; 
  signal SYN16731 : STD_LOGIC; 
  signal SYN16734 : STD_LOGIC; 
  signal SYN16735 : STD_LOGIC; 
  signal SYN16736 : STD_LOGIC; 
  signal SYN16747 : STD_LOGIC; 
  signal SYN16749 : STD_LOGIC; 
  signal SYN16748 : STD_LOGIC; 
  signal SYN16752 : STD_LOGIC;