?? adc0809.tan.rpt
字號:
Timing Analyzer report for ADC0809
Tue Jun 26 09:29:44 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. tpd
9. th
10. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 4.081 ns ; eoc ; current_state.st3 ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 8.656 ns ; regl[0] ; q[0] ; clk ; -- ; 0 ;
; Worst-case tpd ; N/A ; None ; 8.927 ns ; abc_in[2] ; abc_out[2] ; -- ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 2.185 ns ; d[1] ; regl[1] ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; current_state.st5 ; current_state.st6 ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C5T144C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+-------------------+-------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------------+-------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; current_state.st5 ; current_state.st6 ; clk ; clk ; None ; None ; 0.682 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; current_state.st6 ; current_state.st0 ; clk ; clk ; None ; None ; 0.644 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; current_state.st2 ; current_state.st3 ; clk ; clk ; None ; None ; 0.543 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; current_state.st1 ; current_state.st2 ; clk ; clk ; None ; None ; 0.542 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; current_state.st0 ; current_state.st1 ; clk ; clk ; None ; None ; 0.535 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; current_state.st3 ; current_state.st4 ; clk ; clk ; None ; None ; 0.535 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; current_state.st4 ; current_state.st5 ; clk ; clk ; None ; None ; 0.533 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; current_state.st4 ; current_state.st4 ; clk ; clk ; None ; None ; 0.407 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; current_state.st3 ; current_state.st3 ; clk ; clk ; None ; None ; 0.407 ns ;
+-------+------------------------------------------------+-------------------+-------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+-------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+-------------------+----------+
; N/A ; None ; 4.081 ns ; eoc ; current_state.st3 ; clk ;
; N/A ; None ; 4.040 ns ; eoc ; current_state.st4 ; clk ;
; N/A ; None ; 3.935 ns ; eoc ; current_state.st5 ; clk ;
; N/A ; None ; 2.519 ns ; d[6] ; regl[6] ; clk ;
; N/A ; None ; 2.511 ns ; d[7] ; regl[7] ; clk ;
; N/A ; None ; 2.312 ns ; d[4] ; regl[4] ; clk ;
; N/A ; None ; 2.224 ns ; d[5] ; regl[5] ; clk ;
; N/A ; None ; 1.897 ns ; d[3] ; regl[3] ; clk ;
; N/A ; None ; -1.330 ns ; d[2] ; regl[2] ; clk ;
; N/A ; None ; -1.405 ns ; d[0] ; regl[0] ; clk ;
; N/A ; None ; -1.517 ns ; d[1] ; regl[1] ; clk ;
+-------+--------------+------------+------+-------------------+----------+
+----------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------------------+-------+------------+
; N/A ; None ; 8.656 ns ; regl[0] ; q[0] ; clk ;
; N/A ; None ; 7.920 ns ; regl[2] ; q[2] ; clk ;
; N/A ; None ; 7.802 ns ; regl[7] ; q[7] ; clk ;
; N/A ; None ; 7.799 ns ; regl[4] ; q[4] ; clk ;
; N/A ; None ; 7.689 ns ; regl[6] ; q[6] ; clk ;
; N/A ; None ; 7.666 ns ; regl[5] ; q[5] ; clk ;
; N/A ; None ; 7.653 ns ; regl[1] ; q[1] ; clk ;
?? 快捷鍵說明
復(fù)制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -