library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

entity LDPC  is
    Port (
		clock			: in STD_LOGIC;
		-----------------------------------------------------------------
		-- Test Vectors
		-----------------------------------------------------------------
		checkToE0OUT			: out SIGNED (7 downto 0);
		checkToE1OUT			: out SIGNED (7 downto 0);
		checkToE2OUT			: out SIGNED (7 downto 0);
		--checkToBit0				: in SIGNED (7 downto 0);
		--checkToBit1				: in SIGNED (7 downto 0);
		receivedBitsArrayOutput	: out SIGNED (7 downto 0);
		L2Input					: out SIGNED (7 downto 0);
		-----------------------------------------------------------------
		-- Check To Bit Vectors
		-----------------------------------------------------------------
		L2ToCheck0OUT			: out SIGNED (7 downto 0);
		L2ToCheck1OUT			: out SIGNED (7 downto 0);
		L2ToCheck2OUT			: out SIGNED (7 downto 0);
		EOutputAdd				: in STD_LOGIC_VECTOR (1 downto 0);
		EArrayRE				: in STD_LOGIC;
		ERamBankSel				: in STD_LOGIC_VECTOR (1 downto 0);
		EInputAdd				: in STD_LOGIC_VECTOR (1 downto 0);
		EArrayWE				: in STD_LOGIC;
		EToBit0OUT				: out SIGNED (7 downto 0);
		EToBit1OUT				: out SIGNED (7 downto 0);
		EToBit2OUT				: out SIGNED (7 downto 0);
		-----------------------------------------------------------------
		-- Bit To Check Vectors
		-----------------------------------------------------------------
		bitToL20				: out SIGNED (7 downto 0);
		bitToL21				: out SIGNED (7 downto 0);
		L2InputAdd				: in STD_LOGIC_VECTOR (1 downto 0);
		L2OutputAdd				: in STD_LOGIC_VECTOR (1 downto 0);
		L2RamBankSel			: in STD_LOGIC_VECTOR (1 downto 0);
		L2ArrayWE				: in STD_LOGIC;
		L2ArrayRE				: in STD_LOGIC;
		bitToL2InputSel			: in STD_LOGIC;
		L1						: out SIGNED (7 downto 0);
		arrayInitialise			: in STD_LOGIC;
		bitNodeInSel			: in STD_LOGIC;
		checkToBit0OUT			: out SIGNED (7 downto 0);
		checkToBit1OUT			: out SIGNED (7 downto 0);
		-----------------------------------------------------------------
		-- Received Bits Vectors
		-----------------------------------------------------------------
		receivedBitsAdd			: in STD_LOGIC_VECTOR (3 downto 0);
		receivedBitsOutputAdd	: in STD_LOGIC_VECTOR (2 downto 0);
		receivedBits			: in SIGNED (7 downto 0);
		receivedBitsArrayWE		: in STD_LOGIC;
		receivedBitsArrayRE		: in STD_LOGIC
	);
end LDPC;
-----------------------------------------------------------------
-- Architecture Declaration
-----------------------------------------------------------------
architecture Behavioral of LDPC is
	-----------------------------------------------------------------
	-- COMPONENTS
	-----------------------------------------------------------------
	COMPONENT blockLengthRAM
		PORT (
			address		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
			clock		: IN STD_LOGIC ;
			data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			wren		: IN STD_LOGIC  := '1';
			q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
		);
	END COMPONENT;

	COMPONENT L2
	    PORT (
			clock		: IN STD_LOGIC;
			data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			rdaddress	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
			rden		: IN STD_LOGIC;
			ramBankSel	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
			wraddress	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
			wren		: IN STD_LOGIC;
			q0			: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			q1			: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			q2			: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
		);
	END COMPONENT;

	COMPONENT E
	    PORT (
			clock		: IN STD_LOGIC;
			data0		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			data1		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			data2		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			rdaddress	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
			rden		: IN STD_LOGIC;
			wraddress	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
			wren		: IN STD_LOGIC;
			q0			: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			q1			: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			q2			: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
		);
	END COMPONENT;

	COMPONENT bitNode
	    PORT (
			clock	 	: in STD_LOGIC;

			fromCheck0 	: in SIGNED (7 downto 0);
			fromCheck1 	: in SIGNED (7 downto 0);

			toCheck0 	: out SIGNED (7 downto 0);
	        toCheck1 	: out SIGNED (7 downto 0);

			corrected	: out SIGNED (7 downto 0);
			init	 	: in STD_LOGIC;
			received 	: in SIGNED (7 downto 0)
		);
	END COMPONENT;

	COMPONENT checkNode
	    PORT (
			fromBit0 	: in SIGNED (7 downto 0);
			fromBit1 	: in SIGNED (7 downto 0);
	        fromBit2 	: in SIGNED (7 downto 0);

			toBit0	 	: out SIGNED (7 downto 0);
	        toBit1	 	: out SIGNED (7 downto 0);
	        toBit2 		: out SIGNED (7 downto 0)
		);
	END COMPONENT;
	-----------------------------------------------------------------
	-- SIGNALS DECLARATION
	-----------------------------------------------------------------
	-- Received Bits Vectors
	SIGNAL receivedBitsArrayOutputSignal 	: SIGNED (7 downto 0);
	-- Bit To Check Vectors
	SIGNAL bitToL20Signal					: SIGNED (7 downto 0);
	SIGNAL bitToL21Signal	 				: SIGNED (7 downto 0);
	SIGNAL L2InputSignal					: SIGNED (7 downto 0);
	SIGNAL checkToBit0						: SIGNED (7 downto 0);
	SIGNAL checkToBit1						: SIGNED (7 downto 0);
	-- Check To Bit Vectors
	SIGNAL L2ToCheck0						: SIGNED (7 downto 0);
	SIGNAL L2ToCheck1						: SIGNED (7 downto 0);
	SIGNAL L2ToCheck2						: SIGNED (7 downto 0);
	SIGNAL checkToE0						: SIGNED (7 downto 0);
	SIGNAL checkToE1						: SIGNED (7 downto 0);
	SIGNAL checkToE2						: SIGNED (7 downto 0);
	SIGNAL EToBit0							: SIGNED (7 downto 0);
	SIGNAL EToBit1							: SIGNED (7 downto 0);
	SIGNAL EToBit2							: SIGNED (7 downto 0);
-----------------------------------------------------------------
-- Architecture Begin
-----------------------------------------------------------------
begin
	-- Received Bits Vectors
	receivedBitsArrayOutput <= receivedBitsArrayOutputSignal;
	-- Bit To Check Vectors
	bitToL20 <= bitToL20Signal;
	bitToL21 <= bitToL21Signal;
	L2Input <= L2InputSignal;
	EToBit0OUT <= EToBit0;
	EToBit1OUT <= EToBit1;
	EToBit2OUT <= EToBit2;
	checkToBit0OUT <= checkToBit0;
	checkToBit1OUT <= checkToBit1;
	-- Check To Bit Vectors
	L2ToCheck0OUT <= L2ToCheck0;
	L2ToCheck1OUT <= L2ToCheck1;
	L2ToCheck2OUT <= L2ToCheck2;
	checkToE0OUT <= checkToE0;
	checkToE1OUT <= checkToE1;
	checkToE2OUT <= checkToE2;
	-----------------------------------------------------------------
	-- Received Bits Array
	-----------------------------------------------------------------
	R : blockLengthRAM
	PORT MAP (
		address 	=> receivedBitsAdd,
		clock 		=> clock,
		data 		=> STD_LOGIC_VECTOR(receivedBits),
		wren 		=> receivedBitsArrayWE,
		SIGNED(q) 	=> receivedBitsArrayOutputSignal
	);
	-----------------------------------------------------------------
	-- Bit To Check Array
	-----------------------------------------------------------------
	L2Array : L2
    PORT MAP (
		clock 		=> clock,
		data		=> STD_LOGIC_VECTOR(L2InputSignal),
		rdaddress	=> L2OutputAdd,
		rden		=> L2ArrayRE,
		ramBankSel	=> L2RamBankSel,
		wraddress 	=> L2InputAdd,
		wren		=> L2ArrayWE,
		SIGNED(q0)	=> L2ToCheck0,
		SIGNED(q1)	=> L2ToCheck1,
		SIGNED(q2)	=> L2ToCheck2
	);
	-----------------------------------------------------------------
	-- Check To Bit Array
	-----------------------------------------------------------------
	EArray : E
    PORT MAP (
		clock 		=> clock,
		data0		=> STD_LOGIC_VECTOR(checkToE0),
		data1		=> STD_LOGIC_VECTOR(checkToE1),
		data2		=> STD_LOGIC_VECTOR(checkToE2),
		rdaddress	=> EOutputAdd,
		rden		=> EArrayRE,
		wraddress	=> EInputAdd,
		wren		=> EArrayWE,
		SIGNED(q0)	=> EToBit0,
		SIGNED(q1)	=> EToBit1,
		SIGNED(q2)	=> EToBit2
	);

	-----------------------------------------------------------------
	-- Bit Node
	-----------------------------------------------------------------
	bitNode0 : bitNode
    PORT MAP (
		clock		=> clock,

		fromCheck0 	=> checkToBit0,
		fromCheck1 	=> checkToBit1,

		toCheck0	=> bitToL20Signal,
        toCheck1 	=> bitToL21Signal,

		corrected	=> L1,
		init		=> arrayInitialise,
		received	=> receivedBitsArrayOutputSignal
	);
	-----------------------------------------------------------------
	-- Check Node
	-----------------------------------------------------------------
	checkNode0 : checkNode
    PORT MAP (
		fromBit0 	=> L2ToCheck0,
		fromBit1 	=> L2ToCheck1,
        fromBit2 	=> L2ToCheck2,

		toBit0		=> checkToE0,
        toBit1	 	=> checkToE1,
        toBit2 		=> checkToE2
	);

	PROCESS(bitToL2InputSel, bitToL20Signal, bitToL21Signal)
	BEGIN
		--if(clock'event and clock = '1') then
		if(bitToL2InputSel = '0') then
			L2InputSignal <= bitToL20Signal;
		else
			L2InputSignal <= bitToL21Signal;
		end if;
		--end if;
	END PROCESS;
	process(clock, ERamBankSel, bitNodeInSel, EToBit0, EToBit1, EToBit2)
	begin
		if(clock'event and clock = '1') then
			if(bitNodeInSel = '0') then
				if(ERamBankSel = "00") then
					checkToBit0 <= EToBit0;
				elsif(ERamBankSel = "01") then
					checkToBit0 <= EToBit1;
				elsif(ERamBankSel = "10") then
					checkToBit0 <= EToBit2;
				else
					checkToBit0 <= "00000000";
				end if;
			else
				if(ERamBankSel = "00") then
					checkToBit1 <= EToBit0;
				elsif(ERamBankSel = "01") then
					checkToBit1 <= EToBit1;
				elsif(ERamBankSel = "10") then
					checkToBit1 <= EToBit2;
				else
					checkToBit1 <= "00000000";
				end if;
			end if;
		end if;
	end process;
end Behavioral;