; N/A   ; None         ; -0.638 ns  ; din  ; pre_s.s3 ; clk      ;
; N/A   ; None         ; -0.857 ns  ; din  ; pre_s.s0 ; clk      ;
+-------+--------------+------------+------+----------+----------+


+------------------------------------------------------------------+
; tco                                                              ;
+-------+--------------+------------+----------+------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To   ; From Clock ;
+-------+--------------+------------+----------+------+------------+
; N/A   ; None         ; 6.368 ns   ; pre_s.s3 ; dout ; clk        ;
+-------+--------------+------------+----------+------+------------+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To       ; To Clock ;
+---------------+-------------+-----------+------+----------+----------+
; N/A           ; None        ; 1.087 ns  ; din  ; pre_s.s0 ; clk      ;
; N/A           ; None        ; 0.868 ns  ; din  ; pre_s.s3 ; clk      ;
; N/A           ; None        ; 0.865 ns  ; din  ; pre_s.s2 ; clk      ;
; N/A           ; None        ; 0.813 ns  ; din  ; pre_s.s1 ; clk      ;
+---------------+-------------+-----------+------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Oct 03 21:42:32 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mapy -c mapy --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "pre_s.s0" and destination register "pre_s.s1"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.665 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y35_N9; Fanout = 2; REG Node = 'pre_s.s0'
            Info: 2: + IC(0.306 ns) + CELL(0.275 ns) = 0.581 ns; Loc. = LCCOMB_X30_Y35_N0; Fanout = 1; COMB Node = 'Selector1~12'
            Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.665 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 1; REG Node = 'pre_s.s1'
            Info: Total cell delay = 0.359 ns ( 53.98 % )
            Info: Total interconnect delay = 0.306 ns ( 46.02 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.698 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 1; REG Node = 'pre_s.s1'
                Info: Total cell delay = 1.536 ns ( 56.93 % )
                Info: Total interconnect delay = 1.162 ns ( 43.07 % )
            Info: - Longest clock path from clock "clk" to source register is 2.698 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X30_Y35_N9; Fanout = 2; REG Node = 'pre_s.s0'
                Info: Total cell delay = 1.536 ns ( 56.93 % )
                Info: Total interconnect delay = 1.162 ns ( 43.07 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "pre_s.s1" (data pin = "din", clock pin = "clk") is -0.583 ns
    Info: + Longest pin to register delay is 2.151 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 4; PIN Node = 'din'
        Info: 2: + IC(0.668 ns) + CELL(0.420 ns) = 2.067 ns; Loc. = LCCOMB_X30_Y35_N0; Fanout = 1; COMB Node = 'Selector1~12'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.151 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 1; REG Node = 'pre_s.s1'
        Info: Total cell delay = 1.483 ns ( 68.94 % )
        Info: Total interconnect delay = 0.668 ns ( 31.06 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.698 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 1; REG Node = 'pre_s.s1'
        Info: Total cell delay = 1.536 ns ( 56.93 % )
        Info: Total interconnect delay = 1.162 ns ( 43.07 % )
Info: tco from clock "clk" to destination pin "dout" through register "pre_s.s3" is 6.368 ns
    Info: + Longest clock path from clock "clk" to source register is 2.698 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X30_Y35_N23; Fanout = 2; REG Node = 'pre_s.s3'
        Info: Total cell delay = 1.536 ns ( 56.93 % )
        Info: Total interconnect delay = 1.162 ns ( 43.07 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.420 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y35_N23; Fanout = 2; REG Node = 'pre_s.s3'
        Info: 2: + IC(0.632 ns) + CELL(2.788 ns) = 3.420 ns; Loc. = PIN_C12; Fanout = 0; PIN Node = 'dout'
        Info: Total cell delay = 2.788 ns ( 81.52 % )
        Info: Total interconnect delay = 0.632 ns ( 18.48 % )
Info: th for register "pre_s.s0" (data pin = "din", clock pin = "clk") is 1.087 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.698 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X30_Y35_N9; Fanout = 2; REG Node = 'pre_s.s0'
        Info: Total cell delay = 1.536 ns ( 56.93 % )
        Info: Total interconnect delay = 1.162 ns ( 43.07 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 1.877 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 4; PIN Node = 'din'
        Info: 2: + IC(0.664 ns) + CELL(0.150 ns) = 1.793 ns; Loc. = LCCOMB_X30_Y35_N8; Fanout = 1; COMB Node = 'pre_s.s0~8'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 1.877 ns; Loc. = LCFF_X30_Y35_N9; Fanout = 2; REG Node = 'pre_s.s0'
        Info: Total cell delay = 1.213 ns ( 64.62 % )
        Info: Total interconnect delay = 0.664 ns ( 35.38 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Oct 03 21:42:32 2008
    Info: Elapsed time: 00:00:01