tb_ethernet.test_mac_full_duplex_receive.first_fr_received \      tb_ethernet.test_mac_full_duplex_receive.bit_end_1's \      tb_ethernet.test_mac_full_duplex_receive.bit_end_2's \      tb_ethernet.test_mac_full_duplex_receive.bit_start_1's \      tb_ethernet.test_mac_full_duplex_receive.bit_start_2's \      tb_ethernet.test_mac_full_duplex_receive.burst_data[32767:0]'h \      tb_ethernet.test_mac_full_duplex_receive.burst_tmp_data[32767:0]'h \      tb_ethernet.test_mac_full_duplex_receive.check_frame \      tb_ethernet.test_mac_full_duplex_receive.data[31:0]'h \      tb_ethernet.test_mac_full_duplex_receive.end_task[31:0]'h \      tb_ethernet.test_mac_full_duplex_receive.fail's \      tb_ethernet.test_mac_full_duplex_receive.first_fr_received \      tb_ethernet.test_mac_full_duplex_receive.frame_ended \      tb_ethernet.test_mac_full_duplex_receive.frame_started \      tb_ethernet.test_mac_full_duplex_receive.i's \      tb_ethernet.test_mac_full_duplex_receive.i1's \      tb_ethernet.test_mac_full_duplex_receive.i2's \      tb_ethernet.test_mac_full_duplex_receive.i3's \      tb_ethernet.test_mac_full_duplex_receive.i_addr's \      tb_ethernet.test_mac_full_duplex_receive.i_data's \      tb_ethernet.test_mac_full_duplex_receive.i_length's \      tb_ethernet.test_mac_full_duplex_receive.max_tmp[15:0]'h \      tb_ethernet.test_mac_full_duplex_receive.min_tmp[15:0]'h \      tb_ethernet.test_mac_full_duplex_receive.num_of_bd's \      tb_ethernet.test_mac_full_duplex_receive.num_of_frames's \      tb_ethernet.test_mac_full_duplex_receive.num_of_reg's \      tb_ethernet.test_mac_full_duplex_receive.speed's \      tb_ethernet.test_mac_full_duplex_receive.st_data[7:0]'h \      tb_ethernet.test_mac_full_duplex_receive.start_task[31:0]'h \      tb_ethernet.test_mac_full_duplex_receive.stop_checking_frame \      tb_ethernet.test_mac_full_duplex_receive.test_num's \      tb_ethernet.test_mac_full_duplex_receive.tmp[31:0]'h \      tb_ethernet.test_mac_full_duplex_receive.tmp_bd'h \      tb_ethernet.test_mac_full_duplex_receive.tmp_bd_num's \      tb_ethernet.test_mac_full_duplex_receive.tmp_data's \      tb_ethernet.test_mac_full_duplex_receive.tmp_ipgt's \      tb_ethernet.test_mac_full_duplex_receive.tmp_len's \      tb_ethernet.test_mac_full_duplex_receive.tx_bd_num[31:0]'h \      tb_ethernet.test_mac_full_duplex_receive.wait_for_frame \      tb_ethernet.wbm_working \      tb_ethernet.check_rx_packet.addr_phy[31:0]'h \      tb_ethernet.check_rx_packet.addr_wb[31:0]'h \      tb_ethernet.check_rx_packet.buffer[21:0]'h \      tb_ethernet.check_rx_packet.data_phy'h \      tb_ethernet.check_rx_packet.data_wb'h \      tb_ethernet.check_rx_packet.delta_t \      tb_ethernet.check_rx_packet.failure[31:0]'h \      tb_ethernet.check_rx_packet.i's \      tb_ethernet.check_rx_packet.len[15:0]'h \      tb_ethernet.check_rx_packet.plus_dribble_nibble \      tb_ethernet.check_rx_packet.rxpnt_phy[31:0]'h \      tb_ethernet.check_rx_packet.rxpnt_wb[31:0]'h \      tb_ethernet.check_rx_packet.successful_dribble_nibble \      tb_ethernet.wb_slave.rd_mem.adr_i[31:0]'h \      tb_ethernet.wb_slave.rd_mem.dat_o[31:0]'h \      tb_ethernet.wb_slave.rd_mem.sel_i[3:0]'h \      tb_ethernet.wb_slave.ADR_I[31:0]'h \      tb_ethernet.wb_slave.mem_wr_data_out[31:0]'h \      tb_ethernet.wb_slave.SEL_I[3:0]'h \add group \    "MAC FIFO" \      tb_ethernet.eth_top.wishbone.rx_fifo.write \      tb_ethernet.eth_top.wishbone.rx_fifo.data_in[31:0]'h \      tb_ethernet.eth_top.wishbone.rx_fifo.write_pointer[3:0]'h \      tb_ethernet.eth_top.wishbone.rx_fifo.almost_full \      tb_ethernet.eth_top.wishbone.rx_fifo.full \      tb_ethernet.eth_top.wishbone.rx_fifo.read \      tb_ethernet.eth_top.wishbone.rx_fifo.data_out[31:0]'h \      tb_ethernet.eth_top.wishbone.rx_fifo.read_pointer[3:0]'h \      tb_ethernet.eth_top.wishbone.rx_fifo.almost_empty \      tb_ethernet.eth_top.wishbone.rx_fifo.empty \add group \    "MAC registers" \      tb_ethernet.eth_top.ethreg1.MODEROut[31:0]'h \      tb_ethernet.eth_top.ethreg1.INT_SOURCEOut[31:0]'h \      tb_ethernet.eth_top.ethreg1.INT_MASKOut[31:0]'h \      tb_ethernet.eth_top.ethreg1.IPGTOut[31:0]'h \      tb_ethernet.eth_top.ethreg1.IPGR1Out[31:0]'h \      tb_ethernet.eth_top.ethreg1.IPGR2Out[31:0]'h \      tb_ethernet.eth_top.ethreg1.PACKETLENOut[31:0]'h \      tb_ethernet.eth_top.ethreg1.COLLCONFOut[31:0]'h \      tb_ethernet.eth_top.ethreg1.TX_BD_NUMOut[31:0]'h \      tb_ethernet.eth_top.ethreg1.CTRLMODEROut[31:0]'h \      tb_ethernet.eth_top.ethreg1.MIIMODEROut[31:0]'h \      tb_ethernet.eth_top.ethreg1.MIICOMMANDOut[31:0]'h \      tb_ethernet.eth_top.ethreg1.MIIADDRESSOut[31:0]'h \      tb_ethernet.eth_top.ethreg1.MIITX_DATAOut[31:0]'h \      tb_ethernet.eth_top.ethreg1.MIIRX_DATAOut[31:0]'h \      tb_ethernet.eth_top.ethreg1.MIISTATUSOut[31:0]'h \      tb_ethernet.eth_top.ethreg1.MAC_ADDR0Out[31:0]'h \      tb_ethernet.eth_top.ethreg1.MAC_ADDR1Out[31:0]'h \      tb_ethernet.eth_top.ethreg1.HASH0Out[31:0]'h \      tb_ethernet.eth_top.ethreg1.HASH1Out[31:0]'h \      tb_ethernet.eth_top.ethreg1.TXCTRLOut[31:0]'h \add group \    testbench_test_signals \      tb_ethernet.test_mac_full_duplex_transmit.i_length's \      tb_ethernet.test_mac_full_duplex_transmit.tmp_len's \add group \    "MAC common" \      tb_ethernet.eth_top.mcoll_pad_i \      tb_ethernet.eth_top.mcrs_pad_i \add group \    "MAC TX" \      tb_ethernet.eth_top.mtx_clk_pad_i \      tb_ethernet.eth_top.mtxd_pad_o[3:0]'h \      tb_ethernet.eth_top.mtxen_pad_o \      tb_ethernet.eth_top.mtxerr_pad_o \add group \    "MAC RX" \      tb_ethernet.eth_top.mrx_clk_pad_i \      tb_ethernet.eth_top.mrxd_pad_i[3:0]'h \      tb_ethernet.eth_top.mrxdv_pad_i \      tb_ethernet.eth_top.mrxerr_pad_i \add group \    "MAC MIIM interface" \      tb_ethernet.eth_top.mdc_pad_o \      tb_ethernet.eth_top.md_padoe_o \      tb_ethernet.eth_top.md_pad_o \      tb_ethernet.eth_top.md_pad_i \      tb_ethernet.eth_top.miim1.Busy \      tb_ethernet.eth_top.miim1.LinkFail \      tb_ethernet.eth_top.miim1.Nvalid \      tb_ethernet.eth_top.miim1.CtrlData[15:0]'h \      tb_ethernet.eth_top.miim1.UpdateMIIRX_DATAReg \      tb_ethernet.eth_top.miim1.Prsd[15:0]'h \      tb_ethernet.eth_top.miim1.Divider[7:0]'h \add group \    "Test signals" \      tb_ethernet.test_name[799:0]'a \      tb_ethernet.eth_top.miim1.Nvalid \      tb_ethernet.eth_top.miim1.Busy \      tb_ethernet.eth_top.miim1.LinkFail \      tb_ethernet.eth_top.miim1.WriteDataOp \      tb_ethernet.eth_top.miim1.ReadStatusOp \      tb_ethernet.eth_top.miim1.ScanStatusOp \      tb_ethernet.eth_top.ethreg1.MIISTATUSOut[31:0]'h \      tb_ethernet.eth_top.ethreg1.MIITX_DATAOut[31:0]'h \      tb_ethernet.eth_top.ethreg1.MIIRX_DATAOut[31:0]'h \      tb_ethernet.eth_top.ethreg1.MIIMODEROut[31:0]'h \      tb_ethernet.eth_top.miim1.InProgress \      tb_ethernet.eth_top.miim1.InProgress_q1 \      tb_ethernet.eth_top.miim1.InProgress_q2 \      tb_ethernet.eth_top.miim1.InProgress_q3 \      tb_ethernet.eth_top.miim1.shftrg.ShiftReg[7:0]'h \      tb_ethernet.eth_phy.status_bit6_0[6:0]'h \      tb_ethernet.eth_phy.control_bit8_0[8:0]'h \      tb_ethernet.eth_phy.control_bit9 \      tb_ethernet.eth_phy.control_bit14_10[14:10]'h \      tb_ethernet.eth_phy.control_bit15 \      tb_ethernet.eth_phy.eth_speed \      tb_ethernet.eth_phy.m_rst_n_i \      tb_ethernet.eth_phy.mcoll_o \      tb_ethernet.eth_phy.mcrs_o \      tb_ethernet.eth_phy.md_get_phy_address \      tb_ethernet.eth_phy.md_get_reg_address \      tb_ethernet.eth_phy.md_get_reg_data_in \      tb_ethernet.eth_phy.md_put_reg_data_in \      tb_ethernet.eth_phy.md_put_reg_data_out \      tb_ethernet.eth_phy.reg_data_in[15:0]'h \      tb_ethernet.eth_phy.reg_data_out[15:0]'h \      tb_ethernet.eth_phy.register_bus_in[15:0]'h \      tb_ethernet.eth_phy.register_bus_out[15:0]'h \      tb_ethernet.eth_phy.reg_address[4:0]'h \      tb_ethernet.eth_phy.md_io_output \      tb_ethernet.eth_phy.md_io_enable \      tb_ethernet.eth_phy.md_io \      tb_ethernet.Mdc_O \      tb_ethernet.Mdi_I \      tb_ethernet.Mdio_IO \      tb_ethernet.Mdo_O \      tb_ethernet.Mdo_OE \      tb_ethernet.eth_phy.md_io_enable \      tb_ethernet.eth_phy.md_io_output \      tb_ethernet.eth_phy.md_io_rd_wr \      tb_ethernet.eth_phy.md_io_reg \      tb_ethernet.eth_phy.m_rst_n_i \      tb_ethernet.eth_phy.md_transfer_cnt'd \      tb_ethernet.eth_phy.md_transfer_cnt_reset \      tb_ethernet.eth_phy.mdc_i \      tb_ethernet.eth_phy.mrx_clk_o \      tb_ethernet.eth_phy.mrxd_o[3:0]'h \      tb_ethernet.eth_phy.mrxdv_o \      tb_ethernet.eth_phy.mrxerr_o \      tb_ethernet.eth_phy.mtx_clk_o \      tb_ethernet.eth_phy.mtxd_i[3:0]'h \      tb_ethernet.eth_phy.mtxen_i \      tb_ethernet.eth_phy.mtxerr_i \      tb_ethernet.eth_phy.phy_address[4:0]'h \      tb_ethernet.eth_phy.phy_id1[15:0]'h \      tb_ethernet.eth_phy.phy_id2[15:0]'h \      tb_ethernet.eth_phy.phy_log[31:0]'h \      tb_ethernet.eth_phy.reg_address[4:0]'h \      tb_ethernet.eth_phy.register_bus_in[15:0]'h \      tb_ethernet.eth_phy.register_bus_out[15:0]'h \      tb_ethernet.eth_phy.registers_addr_data_test_operation \      tb_ethernet.eth_phy.rx_link_down_halfperiod \        ( \          minmax 0 93 \        ) \      tb_ethernet.eth_phy.self_clear_d0 \      tb_ethernet.eth_phy.self_clear_d1 \      tb_ethernet.eth_phy.self_clear_d2 \      tb_ethernet.eth_phy.self_clear_d3 \      tb_ethernet.eth_phy.status_bit6_0[6:0]'h \      tb_ethernet.eth_phy.status_bit7 \      tb_ethernet.eth_phy.status_bit8 \      tb_ethernet.eth_phy.status_bit15_9[15:9]'h \deselect allopen window designbrowser 1 geometry 56 121 855 550