#!/bin/csh -fset arg_num = $#argv; # number of arguments# current iterrationset iter = 1;# number of tests with DEFINES + test with user defined constants!set all_iterations = 3;# ATS (Automatic Test System) parameter, which causes displaying 'OK'# if all testcases finish OK.set ok = 1;# Process argumentset i = 1;set arg_waves = 0;set arg_regression = 0;if ($arg_num == 0) then            echo "    Verification without any parameter !"else  while ($i <= $arg_num);    if (("$argv[$i]" == "waves") | ("$argv[$i]" == "-w")) then            @ arg_waves = 1;            echo "    Verification with parameter : waves !"    else       if (("$argv[$i]" == "regression") | ("$argv[$i]" == "-r")) then            @ arg_regression = 1;            echo "    Verification with parameter : regression !"      else            echo "    Not correct parameter ( $i )"            echo "    Correct parameters are:"            echo "      'waves' or '-w'"            echo "      'regression' or '-r'"            exit      endif    endif    @ i = $i + 1;  endendif#   if ($arg_num == 1) then#     if (("$1" == "waves") | ("$1" == "-w")) then#             @ arg_waves = 1;#             echo "    Verification with parameter : waves !"#     else#       if (("$1" == "regression") | ("$1" == "-r")) then#             @ arg_regression = 1;#             echo "    Verification with parameter : regression !"#       else#             echo "    Not correct parameter ( $1 )"#             echo "    Correct parameters are:"#             echo "      'waves' or '-w'"#             echo "      'regression' or '-r'"#             exit#       endif#     endif#   else#     if ($arg_num == 2) then#       if (("$1" == "waves") | ("$1" == "-w")) then#             @ arg_waves = 1;#         if (("$2" == "regression") | ("$2" == "-r")) then#             @ arg_regression = 1;#             echo "    Verification with parameter : waves, regression !"#         else#             echo "    Not correct parameter ( $2 )"#             echo "    Correct 2. parameter is:"#             echo "      'regression' or '-r'"#             exit#         endif#       else#         if (("$1" == "regression") | ("$1" == "-r")) then#             @ arg_regression = 1;#           if (("$2" == "waves") | ("$2" == "-w")) then #             @ arg_waves = 1;#             echo "    Verification with parameter : waves, regression !"#           else#             echo "    Not correct parameter ( $2 )"#             echo "    Correct 2. parameter is:"#             echo "      'waves' or '-w'"#             exit#           endif#         else#             echo "    Not correct parameter ( $1 )"#             echo "    Correct parameters are:"#             echo "      'waves' or '-w'"#             echo "      'regression' or '-r'"#             exit#         endif#       endif#     else#             echo "    Too many parameters ( $arg_num )"#             echo "    Maximum number of parameters is 2:"#             echo "      'waves' or '-w'"#             echo "      'regression' or '-r'"#             exit#     endif#   endif# endifecho ""echo "<<<"echo "<<< Ethernet MAC VERIFICATION "echo "<<<" # ITERATION LOOPiteration: echo ""echo "<<<"echo "<<< Iteration ${iter}"echo "<<<"if ($arg_regression == 1) then  if ($iter <= $all_iterations) then    if ($iter == 1) then        echo "<<< Defines:"        echo "\tEthernet with GENERIC RAM"        echo "-DEFINE REGR" > ./defines.args    endif    if ($iter == 2) then        echo "<<< Defines:"        echo "\tEthernet with XILINX DISTRIBUTED RAM"        echo "-DEFINE REGR -DEFINE ETH_FIFO_XILINX" > ./defines.args    endif    if ($iter == 3) then        echo "<<< Defines:"        echo "\tEthernet with XILINX BLOCK RAM"        echo "-DEFINE REGR -DEFINE XILINX_RAMB4" > ./defines.args    endif  endifendif# Run NC-Verilog compilerecho ""echo "\t@@@"echo "\t@@@ Compiling sources"echo "\t@@@"# creating .args file for ncvlog and adding main parametersecho "-cdslib ../bin/cds.lib" > ./ncvlog.argsecho "-hdlvar ../bin/hdl.var" >> ./ncvlog.argsecho "-logfile ../log/ncvlog.log" >> ./ncvlog.argsecho "-update" >> ./ncvlog.argsecho "-messages" >> ./ncvlog.argsecho "-INCDIR ../../../../bench/verilog" >> ./ncvlog.argsecho "-INCDIR ../../../../rtl/verilog" >> ./ncvlog.argsecho "-DEFINE SIM" >> ./ncvlog.args# adding defines to .args fileif ($arg_regression == 1) then    cat ./defines.args >> ./ncvlog.argsendif# adding RTL and Sim files to .args filecat ../bin/rtl_file_list.lst >> ./ncvlog.argscat ../bin/sim_file_list.lst >> ./ncvlog.args                                                                                   # adding device dependent files to .args filecat ../bin/xilinx_file_list.lst >> ./ncvlog.argscat ../bin/artisan_file_list.lst >> ./ncvlog.argsncvlog -file ./ncvlog.args# > /dev/null;echo ""# Run the NC-Verilog elaborator (build the design hierarchy)echo ""echo "\t@@@"echo "\t@@@ Building design hierarchy (elaboration)"echo "\t@@@"ncelab -file ../bin/ncelab_xilinx.args# > /dev/null;echo ""# Run the NC-Verilog simulator (simulate the design)echo ""echo "\t###"echo "\t### Running tests (this takes a long time!)"echo "\t###"# creating ncsim.args file for ncsim and adding main parametersecho "-cdslib ../bin/cds.lib" > ./ncsim.argsecho "-hdlvar ../bin/hdl.var" >> ./ncsim.argsecho "-logfile ../log/ncsim.log" >> ./ncsim.argsecho "-messages" >> ./ncsim.argsif ($arg_waves == 1) then  echo "-input ../bin/ncsim_waves.rc" >> ./ncsim.argselse  echo "-input ../bin/ncsim.rc" >> ./ncsim.args endifecho "worklib.ethernet:fun" >> ./ncsim.argsncsim -file ./ncsim.args > ../log/tb_eth_display.log #| tee ../log/tb_eth_display.logif ($status != 0) then  echo ""  echo "TESTS couldn't start due to Errors!"  echo ""  exitelse  if ($arg_regression == 1) then    if ($arg_waves == 1) then      mv ../out/waves.shm ../out/i${iter}_waves.shm    endif    # For ATS - counting all 'FAILED' words    set FAIL_COUNT = `grep -c "FAILED" ../log/eth_tb.log`    if ($FAIL_COUNT != 0) then        # Test didn't pass!!!        @ ok = 0;    endif    # Move 'log' files    mv ../log/eth_tb.log ../log/i${iter}_eth_tb.log    mv ../log/eth_tb_phy.log ../log/i${iter}_eth_tb_phy.log    mv ../log/eth_tb_memory.log ../log/i${iter}_eth_tb_memory.log    mv ../log/eth_tb_host.log ../log/i${iter}_eth_tb_host.log    mv ../log/eth_tb_wb_s_mon.log ../log/i${iter}_eth_tb_wb_s_mon.log    mv ../log/eth_tb_wb_m_mon.log ../log/i${iter}_eth_tb_wb_m_mon.log  endifendifecho "" @ iter += 1; if (($arg_regression == 1) && ($iter <= $all_iterations)) then    goto iterationelse#   rm ./defines.args    echo ""    echo "<<<"    echo "<<< End of VERIFICATION"    echo "<<<"    echo "<<<"    echo "<<< -------------------------------------------------"    echo "<<<"    # For ATS - displaying 'OK' when tests pass successfuly    echo " "    echo "Simulation finished:"    if ($ok == 1) then        echo "OK"    else        echo "FAILED"    endifendif