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# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.

# Quartus II: Generate Tcl File for Project
# File: sec_clock.tcl
# Generated on: Wed Oct 08 19:46:15 2008

# Load Quartus II Tcl Project package
package require ::quartus::project

set need_to_close_project 0
set make_assignments 1

# Check that the right project is open
if {[is_project_open]} {
	if {[string compare $quartus(project) "sec_clock"]} {
		puts "Project sec_clock is not open"
		set make_assignments 0
	}
} else {
	# Only open if not already open
	if {[project_exists sec_clock]} {
		project_open -revision sec_clock sec_clock
	} else {
		project_new -revision sec_clock sec_clock
	}
	set need_to_close_project 1
}

# Make assignments
if {$make_assignments} {
	set_global_assignment -name FAMILY Cyclone
	set_global_assignment -name DEVICE EP1C3T144C8
	set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
	set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:40:20  OCTOBER 08, 2008"
	set_global_assignment -name LAST_QUARTUS_VERSION 7.2
	set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
	set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
	set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
	set_global_assignment -name VHDL_FILE sec_clock.vhd
	set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
	set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
	set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
	set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
	set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
	
	set_location_assignment PIN_93 -to clk
	set_location_assignment PIN_76 -to rst
	set_location_assignment PIN_91 -to start
	
    set_location_assignment PIN_123 -to data[7]
	set_location_assignment PIN_124 -to data[6]
	set_location_assignment PIN_126 -to data[5]
	set_location_assignment PIN_127 -to data[4]
	set_location_assignment PIN_128 -to data[3]
	set_location_assignment PIN_129 -to data[2]
	set_location_assignment PIN_130 -to data[1]
	set_location_assignment PIN_131 -to data[0]
	
	set_location_assignment PIN_144 -to sel[7]
	set_location_assignment PIN_143 -to sel[6]
	set_location_assignment PIN_142 -to sel[5]
	set_location_assignment PIN_141 -to sel[4]
	set_location_assignment PIN_140 -to sel[3]
	set_location_assignment PIN_139 -to sel[2]
	set_location_assignment PIN_133 -to sel[1]
	set_location_assignment PIN_132 -to sel[0]

	# Commit assignments
	export_assignments

	# Close project
	if {$need_to_close_project} {
		project_close
	}
}