{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 4 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "rst " "Info: Assuming node \"rst\" is an undefined clock" {  } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 5 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "rst" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "start " "Info: Assuming node \"start\" is an undefined clock" {  } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 6 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "start" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk1 " "Info: Detected ripple clock \"clk1\" as buffer" {  } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 11 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register led_6\[1\] register led_2\[2\] 160.59 MHz 6.227 ns Internal " "Info: Clock \"clk\" has Internal fmax of 160.59 MHz between source register \"led_6\[1\]\" and destination register \"led_2\[2\]\" (period= 6.227 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.966 ns + Longest register register " "Info: + Longest register to register delay is 5.966 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led_6\[1\] 1 REG LC_X19_Y7_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y7_N9; Fanout = 5; REG Node = 'led_6\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led_6[1] } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.585 ns) + CELL(0.590 ns) 1.175 ns Equal3~42 2 COMB LC_X19_Y7_N2 3 " "Info: 2: + IC(0.585 ns) + CELL(0.590 ns) = 1.175 ns; Loc. = LC_X19_Y7_N2; Fanout = 3; COMB Node = 'Equal3~42'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.175 ns" { led_6[1] Equal3~42 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.155 ns) + CELL(0.590 ns) 2.920 ns led_4~630 3 COMB LC_X17_Y7_N7 9 " "Info: 3: + IC(1.155 ns) + CELL(0.590 ns) = 2.920 ns; Loc. = LC_X17_Y7_N7; Fanout = 9; COMB Node = 'led_4~630'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.745 ns" { Equal3~42 led_4~630 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.292 ns) 3.677 ns led_2~361 4 COMB LC_X17_Y7_N4 3 " "Info: 4: + IC(0.465 ns) + CELL(0.292 ns) = 3.677 ns; Loc. = LC_X17_Y7_N4; Fanout = 3; COMB Node = 'led_2~361'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.757 ns" { led_4~630 led_2~361 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.454 ns) + CELL(0.292 ns) 4.423 ns led_2~362 5 COMB LC_X17_Y7_N5 2 " "Info: 5: + IC(0.454 ns) + CELL(0.292 ns) = 4.423 ns; Loc. = LC_X17_Y7_N5; Fanout = 2; COMB Node = 'led_2~362'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.746 ns" { led_2~361 led_2~362 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.234 ns) + CELL(0.309 ns) 5.966 ns led_2\[2\] 6 REG LC_X17_Y6_N0 4 " "Info: 6: + IC(1.234 ns) + CELL(0.309 ns) = 5.966 ns; Loc. = LC_X17_Y6_N0; Fanout = 4; REG Node = 'led_2\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.543 ns" { led_2~362 led_2[2] } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.073 ns ( 34.75 % ) " "Info: Total cell delay = 2.073 ns ( 34.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.893 ns ( 65.25 % ) " "Info: Total interconnect delay = 3.893 ns ( 65.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.966 ns" { led_6[1] Equal3~42 led_4~630 led_2~361 led_2~362 led_2[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.966 ns" { led_6[1] {} Equal3~42 {} led_4~630 {} led_2~361 {} led_2~362 {} led_2[2] {} } { 0.000ns 0.585ns 1.155ns 0.465ns 0.454ns 1.234ns } { 0.000ns 0.590ns 0.590ns 0.292ns 0.292ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.675 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.675 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 34 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 34; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns clk1 2 REG LC_X7_Y5_N2 33 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y5_N2; Fanout = 33; REG Node = 'clk1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk clk1 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.010 ns) + CELL(0.711 ns) 7.675 ns led_2\[2\] 3 REG LC_X17_Y6_N0 4 " "Info: 3: + IC(4.010 ns) + CELL(0.711 ns) = 7.675 ns; Loc. = LC_X17_Y6_N0; Fanout = 4; REG Node = 'led_2\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.721 ns" { clk1 led_2[2] } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.59 % ) " "Info: Total cell delay = 3.115 ns ( 40.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.560 ns ( 59.41 % ) " "Info: Total interconnect delay = 4.560 ns ( 59.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.675 ns" { clk clk1 led_2[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.675 ns" { clk {} clk~out0 {} clk1 {} led_2[2] {} } { 0.000ns 0.000ns 0.550ns 4.010ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.675 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.675 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 34 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 34; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns clk1 2 REG LC_X7_Y5_N2 33 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y5_N2; Fanout = 33; REG Node = 'clk1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk clk1 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.010 ns) + CELL(0.711 ns) 7.675 ns led_6\[1\] 3 REG LC_X19_Y7_N9 5 " "Info: 3: + IC(4.010 ns) + CELL(0.711 ns) = 7.675 ns; Loc. = LC_X19_Y7_N9; Fanout = 5; REG Node = 'led_6\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.721 ns" { clk1 led_6[1] } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.59 % ) " "Info: Total cell delay = 3.115 ns ( 40.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.560 ns ( 59.41 % ) " "Info: Total interconnect delay = 4.560 ns ( 59.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.675 ns" { clk clk1 led_6[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.675 ns" { clk {} clk~out0 {} clk1 {} led_6[1] {} } { 0.000ns 0.000ns 0.550ns 4.010ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.675 ns" { clk clk1 led_2[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.675 ns" { clk {} clk~out0 {} clk1 {} led_2[2] {} } { 0.000ns 0.000ns 0.550ns 4.010ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.675 ns" { clk clk1 led_6[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.675 ns" { clk {} clk~out0 {} clk1 {} led_6[1] {} } { 0.000ns 0.000ns 0.550ns 4.010ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 60 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 60 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.966 ns" { led_6[1] Equal3~42 led_4~630 led_2~361 led_2~362 led_2[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.966 ns" { led_6[1] {} Equal3~42 {} led_4~630 {} led_2~361 {} led_2~362 {} led_2[2] {} } { 0.000ns 0.585ns 1.155ns 0.465ns 0.454ns 1.234ns } { 0.000ns 0.590ns 0.590ns 0.292ns 0.292ns 0.309ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.675 ns" { clk clk1 led_2[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.675 ns" { clk {} clk~out0 {} clk1 {} led_2[2] {} } { 0.000ns 0.000ns 0.550ns 4.010ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.675 ns" { clk clk1 led_6[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.675 ns" { clk {} clk~out0 {} clk1 {} led_6[1] {} } { 0.000ns 0.000ns 0.550ns 4.010ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}