{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 4 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "rst " "Info: Assuming node \"rst\" is an undefined clock" {  } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 5 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "rst" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "start " "Info: Assuming node \"start\" is an undefined clock" {  } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 6 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "start" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk1 " "Info: Detected ripple clock \"clk1\" as buffer" {  } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 11 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register num\[0\] register num\[16\] 166.42 MHz 6.009 ns Internal " "Info: Clock \"clk\" has Internal fmax of 166.42 MHz between source register \"num\[0\]\" and destination register \"num\[16\]\" (period= 6.009 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.748 ns + Longest register register " "Info: + Longest register to register delay is 5.748 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns num\[0\] 1 REG LC_X8_Y5_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y5_N1; Fanout = 4; REG Node = 'num\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { num[0] } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.590 ns) 1.132 ns LessThan0~280 2 COMB LC_X8_Y5_N0 1 " "Info: 2: + IC(0.542 ns) + CELL(0.590 ns) = 1.132 ns; Loc. = LC_X8_Y5_N0; Fanout = 1; COMB Node = 'LessThan0~280'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { num[0] LessThan0~280 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.099 ns) + CELL(0.114 ns) 2.345 ns LessThan0~281 3 COMB LC_X7_Y5_N2 1 " "Info: 3: + IC(1.099 ns) + CELL(0.114 ns) = 2.345 ns; Loc. = LC_X7_Y5_N2; Fanout = 1; COMB Node = 'LessThan0~281'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.213 ns" { LessThan0~280 LessThan0~281 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.641 ns LessThan0~282 4 COMB LC_X7_Y5_N3 1 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 2.641 ns; Loc. = LC_X7_Y5_N3; Fanout = 1; COMB Node = 'LessThan0~282'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { LessThan0~281 LessThan0~282 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.937 ns LessThan0~283 5 COMB LC_X7_Y5_N4 1 " "Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 2.937 ns; Loc. = LC_X7_Y5_N4; Fanout = 1; COMB Node = 'LessThan0~283'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { LessThan0~282 LessThan0~283 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.340 ns) + CELL(0.114 ns) 3.391 ns LessThan0~285 6 COMB LC_X7_Y5_N5 20 " "Info: 6: + IC(0.340 ns) + CELL(0.114 ns) = 3.391 ns; Loc. = LC_X7_Y5_N5; Fanout = 20; COMB Node = 'LessThan0~285'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.454 ns" { LessThan0~283 LessThan0~285 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.245 ns) + CELL(1.112 ns) 5.748 ns num\[16\] 7 REG LC_X8_Y4_N7 4 " "Info: 7: + IC(1.245 ns) + CELL(1.112 ns) = 5.748 ns; Loc. = LC_X8_Y4_N7; Fanout = 4; REG Node = 'num\[16\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.357 ns" { LessThan0~285 num[16] } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.158 ns ( 37.54 % ) " "Info: Total cell delay = 2.158 ns ( 37.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.590 ns ( 62.46 % ) " "Info: Total interconnect delay = 3.590 ns ( 62.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.748 ns" { num[0] LessThan0~280 LessThan0~281 LessThan0~282 LessThan0~283 LessThan0~285 num[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.748 ns" { num[0] {} LessThan0~280 {} LessThan0~281 {} LessThan0~282 {} LessThan0~283 {} LessThan0~285 {} num[16] {} } { 0.000ns 0.542ns 1.099ns 0.182ns 0.182ns 0.340ns 1.245ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.114ns 0.114ns 1.112ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.730 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 34 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 34; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns num\[16\] 2 REG LC_X8_Y4_N7 4 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X8_Y4_N7; Fanout = 4; REG Node = 'num\[16\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { clk num[16] } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk num[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk {} clk~out0 {} num[16] {} } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.730 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 34 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 34; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns num\[0\] 2 REG LC_X8_Y5_N1 4 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X8_Y5_N1; Fanout = 4; REG Node = 'num\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { clk num[0] } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk num[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk {} clk~out0 {} num[0] {} } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk num[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk {} clk~out0 {} num[16] {} } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk num[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk {} clk~out0 {} num[0] {} } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.748 ns" { num[0] LessThan0~280 LessThan0~281 LessThan0~282 LessThan0~283 LessThan0~285 num[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.748 ns" { num[0] {} LessThan0~280 {} LessThan0~281 {} LessThan0~282 {} LessThan0~283 {} LessThan0~285 {} num[16] {} } { 0.000ns 0.542ns 1.099ns 0.182ns 0.182ns 0.340ns 1.245ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.114ns 0.114ns 1.112ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk num[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk {} clk~out0 {} num[16] {} } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk num[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk {} clk~out0 {} num[0] {} } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}