{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 19 23:02:19 2006 " "Info: Processing started: Sun Nov 19 23:02:19 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PS2 -c PS2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PS2 -c PS2" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PS2.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file PS2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 PS2 " "Info: Found entity 1: PS2" {  } { { "PS2.bdf" "" { Schematic "D:/Verilog_PS2_1c12/PS2.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "data_scanC.v(25) " "Warning (10268): Verilog HDL information at data_scanC.v(25): Always Construct contains both blocking and non-blocking assignments" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 25 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_scanC.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file data_scanC.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_scanC " "Info: Found entity 1: data_scanC" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "convert.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file convert.v" { { "Info" "ISGN_ENTITY_NAME" "1 convert " "Info: Found entity 1: convert" {  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mydff.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mydff.v" { { "Info" "ISGN_ENTITY_NAME" "1 mydff " "Info: Found entity 1: mydff" {  } { { "mydff.v" "" { Text "D:/Verilog_PS2_1c12/mydff.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "segmain.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file segmain.v" { { "Info" "ISGN_ENTITY_NAME" "1 segmain " "Info: Found entity 1: segmain" {  } { { "segmain.v" "" { Text "D:/Verilog_PS2_1c12/segmain.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bin27seg.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file bin27seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin27seg " "Info: Found entity 1: bin27seg" {  } { { "bin27seg.v" "" { Text "D:/Verilog_PS2_1c12/bin27seg.v" 14 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "PS2 " "Info: Elaborating entity \"PS2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_DIMENSION" "" "Warning: Found inconsistent dimensions" {  } { { "PS2.bdf" "" { Schematic "D:/Verilog_PS2_1c12/PS2.bdf" { { 56 248 309 72 "data\[15..8\]" "" } { 72 472 527 88 "data\[7..0\]" "" } { 240 -24 48 256 "data\[15..0\]" "" } { 80 -104 64 96 "data" "" } } } }  } 0 0 "Found inconsistent dimensions" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "ZHJS data_scanC inst " "Warning: Port \"ZHJS\" of type data_scanC and instance \"inst\" is missing source signal" {  } { { "PS2.bdf" "" { Schematic "D:/Verilog_PS2_1c12/PS2.bdf" { { 40 112 248 168 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "PA data_scanC inst " "Warning: Port \"PA\" of type data_scanC and instance \"inst\" is missing source signal" {  } { { "PS2.bdf" "" { Schematic "D:/Verilog_PS2_1c12/PS2.bdf" { { 40 112 248 168 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segmain segmain:inst9 " "Info: Elaborating entity \"segmain\" for hierarchy \"segmain:inst9\"" {  } { { "PS2.bdf" "inst9" { Schematic "D:/Verilog_PS2_1c12/PS2.bdf" { { 192 48 224 288 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 segmain.v(29) " "Warning (10230): Verilog HDL assignment warning at segmain.v(29): truncated value with size 32 to match size of target (2)" {  } { { "segmain.v" "" { Text "D:/Verilog_PS2_1c12/segmain.v" 29 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "datain segmain.v(44) " "Warning (10235): Verilog HDL Always Construct warning at segmain.v(44): variable \"datain\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "segmain.v" "" { Text "D:/Verilog_PS2_1c12/segmain.v" 44 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "datain segmain.v(45) " "Warning (10235): Verilog HDL Always Construct warning at segmain.v(45): variable \"datain\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "segmain.v" "" { Text "D:/Verilog_PS2_1c12/segmain.v" 45 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "datain segmain.v(46) " "Warning (10235): Verilog HDL Always Construct warning at segmain.v(46): variable \"datain\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "segmain.v" "" { Text "D:/Verilog_PS2_1c12/segmain.v" 46 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "datain segmain.v(47) " "Warning (10235): Verilog HDL Always Construct warning at segmain.v(47): variable \"datain\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "segmain.v" "" { Text "D:/Verilog_PS2_1c12/segmain.v" 47 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_counter0.vhd 2 1 " "Warning: Using design file lpm_counter0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_counter0-SYN " "Info: Found design unit 1: lpm_counter0-SYN" {  } { { "lpm_counter0.vhd" "" { Text "D:/Verilog_PS2_1c12/lpm_counter0.vhd" 48 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter0 " "Info: Found entity 1: lpm_counter0" {  } { { "lpm_counter0.vhd" "" { Text "D:/Verilog_PS2_1c12/lpm_counter0.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter0 lpm_counter0:inst5 " "Info: Elaborating entity \"lpm_counter0\" for hierarchy \"lpm_counter0:inst5\"" {  } { { "PS2.bdf" "inst5" { Schematic "D:/Verilog_PS2_1c12/PS2.bdf" { { 336 56 200 400 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../altera/quartus51/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../altera/quartus51/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter lpm_counter0:inst5\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"lpm_counter0:inst5\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.vhd" "lpm_counter_component" { Text "D:/Verilog_PS2_1c12/lpm_counter0.vhd" 70 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}