;     -- INPUT_A_FIXED_VALUE            ; Bx                            ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                            ;
+---------------------------------------+-------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Tue Jan 15 12:38:27 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DA_TLC5620 -c DA_TLC5620
Info: Found 1 design units, including 1 entities, in source file DA_TLC5620.bdf
    Info: Found entity 1: DA_TLC5620
Info: Found 1 design units, including 1 entities, in source file tlc5620.v
    Info: Found entity 1: tlc5620
Info: Found 1 design units, including 1 entities, in source file dac_test.v
    Info: Found entity 1: dac_test
Info: Elaborating entity "DA_TLC5620" for the top level hierarchy
Info: Elaborating entity "tlc5620" for hierarchy "tlc5620:inst"
Info: Elaborating entity "dac_test" for hierarchy "dac_test:inst1"
Warning (10230): Verilog HDL assignment warning at dac_test.v(103): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at dac_test.v(104): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at dac_test.v(105): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at dac_test.v(106): truncated value with size 32 to match size of target (8)
Info (10041): Inferred latch for "datain[4][0]" at dac_test.v(87)
Info (10041): Inferred latch for "datain[4][1]" at dac_test.v(87)
Info (10041): Inferred latch for "datain[4][2]" at dac_test.v(87)
Info (10041): Inferred latch for "datain[4][3]" at dac_test.v(87)
Info (10041): Inferred latch for "datain[5][0]" at dac_test.v(87)
Info (10041): Inferred latch for "datain[5][1]" at dac_test.v(87)
Info (10041): Inferred latch for "datain[5][2]" at dac_test.v(87)
Info (10041): Inferred latch for "datain[5][3]" at dac_test.v(87)
Info (10041): Inferred latch for "datain[6][0]" at dac_test.v(87)
Info (10041): Inferred latch for "datain[6][1]" at dac_test.v(87)
Info (10041): Inferred latch for "datain[6][2]" at dac_test.v(87)
Info (10041): Inferred latch for "datain[6][3]" at dac_test.v(87)
Info (10041): Inferred latch for "datain[7][0]" at dac_test.v(87)
Info (10041): Inferred latch for "datain[7][1]" at dac_test.v(87)
Info (10041): Inferred latch for "datain[7][2]" at dac_test.v(87)
Info (10041): Inferred latch for "datain[7][3]" at dac_test.v(87)
Info: Inferred 8 megafunctions from design logic
    Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "dac_test:inst1|Mult0"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "dac_test:inst1|Div0"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "dac_test:inst1|Mod1"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "dac_test:inst1|Div1"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "dac_test:inst1|Mod2"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "dac_test:inst1|Mod0"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "dac_test:inst1|Div2"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "dac_test:inst1|Mod3"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/72/quartus/libraries/megafunctions/lpm_mult.tdf
    Info: Found entity 1: lpm_mult
Info: Elaborated megafunction instantiation "dac_test:inst1|lpm_mult:Mult0"
Info: Found 1 design units, including 1 entities, in source file db/mult_9111.tdf
    Info: Found entity 1: mult_9111
Info: Found 1 design units, including 1 entities, in source file ../../../altera/72/quartus/libraries/megafunctions/lpm_divide.tdf
    Info: Found entity 1: lpm_divide
Info: Elaborated megafunction instantiation "dac_test:inst1|lpm_divide:Div0"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_eem.tdf
    Info: Found entity 1: lpm_divide_eem
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_olh.tdf
    Info: Found entity 1: sign_div_unsign_olh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_h2f.tdf
    Info: Found entity 1: alt_u_div_h2f
Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf
    Info: Found entity 1: add_sub_lkc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf
    Info: Found entity 1: add_sub_mkc
Info: Elaborated megafunction instantiation "dac_test:inst1|lpm_divide:Mod1"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_g6m.tdf
    Info: Found entity 1: lpm_divide_g6m
Info: Elaborated megafunction instantiation "dac_test:inst1|lpm_divide:Div1"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_gem.tdf
    Info: Found entity 1: lpm_divide_gem
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_qlh.tdf
    Info: Found entity 1: sign_div_unsign_qlh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_m2f.tdf
    Info: Found entity 1: alt_u_div_m2f
Info: Elaborated megafunction instantiation "dac_test:inst1|lpm_divide:Div2"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_qfm.tdf
    Info: Found entity 1: lpm_divide_qfm
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_4nh.tdf
    Info: Found entity 1: sign_div_unsign_4nh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_a5f.tdf
    Info: Found entity 1: alt_u_div_a5f
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "78leddata[7]" stuck at VCC
Info: 17 registers lost all their fanouts during netlist optimizations. The first 17 are displayed below.
    Info: Register "dac_test:inst1|count[15]" lost all its fanouts during netlist optimizations.
    Info: Register "dac_test:inst1|count[16]" lost all its fanouts during netlist optimizations.
    Info: Register "dac_test:inst1|count[17]" lost all its fanouts during netlist optimizations.
    Info: Register "dac_test:inst1|count[18]" lost all its fanouts during netlist optimizations.
    Info: Register "dac_test:inst1|count[19]" lost all its fanouts during netlist optimizations.
    Info: Register "dac_test:inst1|count[20]" lost all its fanouts during netlist optimizations.
    Info: Register "dac_test:inst1|count[21]" lost all its fanouts during netlist optimizations.
    Info: Register "dac_test:inst1|count[22]" lost all its fanouts during netlist optimizations.
    Info: Register "dac_test:inst1|count[23]" lost all its fanouts during netlist optimizations.
    Info: Register "dac_test:inst1|count[24]" lost all its fanouts during netlist optimizations.
    Info: Register "dac_test:inst1|count[25]" lost all its fanouts during netlist optimizations.
    Info: Register "dac_test:inst1|count[26]" lost all its fanouts during netlist optimizations.
    Info: Register "dac_test:inst1|count[27]" lost all its fanouts during netlist optimizations.
    Info: Register "dac_test:inst1|count[28]" lost all its fanouts during netlist optimizations.
    Info: Register "dac_test:inst1|count[29]" lost all its fanouts during netlist optimizations.
    Info: Register "dac_test:inst1|count[30]" lost all its fanouts during netlist optimizations.
    Info: Register "dac_test:inst1|count[31]" lost all its fanouts during netlist optimizations.
Info: Found the following redundant logic cells in design
    Info (17048): Logic cell "dac_test:inst1|lpm_divide:Mod2|lpm_divide_g6m:auto_generated|sign_div_unsign_olh:divider|alt_u_div_h2f:divider|add_sub_12_result_int[0]~12"
    Info (17048): Logic cell "dac_test:inst1|lpm_divide:Mod2|lpm_divide_g6m:auto_generated|sign_div_unsign_olh:divider|alt_u_div_h2f:divider|add_sub_9_result_int[0]~22"
    Info (17048): Logic cell "dac_test:inst1|lpm_divide:Mod2|lpm_divide_g6m:auto_generated|sign_div_unsign_olh:divider|alt_u_div_h2f:divider|add_sub_10_result_int[0]~22"
    Info (17048): Logic cell "dac_test:inst1|lpm_divide:Mod2|lpm_divide_g6m:auto_generated|sign_div_unsign_olh:divider|alt_u_div_h2f:divider|add_sub_11_result_int[0]~22"
    Info (17048): Logic cell "dac_test:inst1|lpm_divide:Mod3|lpm_divide_g6m:auto_generated|sign_div_unsign_olh:divider|alt_u_div_h2f:divider|add_sub_12_result_int[0]~12"
Info: Generated suppressed messages file G:/Q71/verilog/DA_TLC5620/DA_TLC5620.map.smsg
Info: Implemented 856 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 20 output pins
    Info: Implemented 828 logic cells
    Info: Implemented 2 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Allocated 150 megabytes of memory during processing
    Info: Processing ended: Tue Jan 15 12:38:33 2008
    Info: Elapsed time: 00:00:06


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in G:/Q71/verilog/DA_TLC5620/DA_TLC5620.map.smsg.