////  Copyright (c) 2003 Launchbird Design Systems, Inc.//  All rights reserved.//  //  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met://    Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.//    Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.//  //  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,//  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.//  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,//  OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;//  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.//  //  //  Overview://  //    Performs a radix 2 Fast Fourier Transform.//    The FFT architecture is pipelined on a rank basis; each rank has its own butterfly and ranks are//    isolated from each other using memory interleavers.  This FFT can perform calcualations on continuous//    streaming data (one data set right after another).  More over, inputs and outputs are passed in pairs,//    doubling the bandwidth.  For instance, a 2048 point FFT can perform a transform every 1024 cycles.//  //  Interface://  //    Synchronization://      clock_c  : Clock input.//      enable_i : Synchronous enable.//      reset_i  : Synchronous reset.//  //    Inputs://      sync_i     : Input sync pulse must occur one frame prior to data input.//      data_0_i   : Input data 0.  Width is 2 * precision.  Real on the left, imag on the right.//      data_1_i   : Input data 1.  Width is 2 * precision.  Real on the left, imag on the right.//  //    Outputs://      sync_o     : Output sync pulse occurs one frame before data output.//      data_0_o   : Output data 0.  Width is 2 * precision.  Real on the left, imag on the right.//      data_1_o   : Output data 1.  Width is 2 * precision.  Real on the left, imag on the right.//  //  Built In Parameters://  //    FFT Points   = 1024//    Precision    = 8//  //  //  //  //  Generated by Confluence 0.6.3  --  Launchbird Design Systems, Inc.  --  www.launchbird.com//  //  Build Date : Fri Aug 22 08:42:00 CDT 2003//  //  Interface//  //    Build Name    : cf_fft_1024_8//    Clock Domains : clock_c  //    Vector Input  : enable_i(1)//    Vector Input  : reset_i(1)//    Vector Input  : sync_i(1)//    Vector Input  : data_0_i(16)//    Vector Input  : data_1_i(16)//    Vector Output : sync_o(1)//    Vector Output : data_0_o(16)//    Vector Output : data_1_o(16)//  //  //  `timescale 1 ns / 1 nsmodule cf_fft_1024_8 (clock_c, enable_i, reset_i, sync_i, data_0_i, data_1_i, sync_o, data_0_o, data_1_o);input  clock_c;input  enable_i;input  reset_i;input  sync_i;input  [15:0] data_0_i;input  [15:0] data_1_i;output sync_o;output [15:0] data_0_o;output [15:0] data_1_o;wire   n1;wire   [15:0] n2;wire   [15:0] n3;cf_fft_1024_8_1 s1 (clock_c, sync_i, data_0_i, data_1_i, enable_i, reset_i, n1, n2, n3);assign sync_o = n1;assign data_0_o = n2;assign data_1_o = n3;endmodulemodule cf_fft_1024_8_1 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);input  clock_c;input  i1;input  [15:0] i2;input  [15:0] i3;input  i4;input  i5;output o1;output [15:0] o2;output [15:0] o3;wire   s1_1;wire   [15:0] s1_2;wire   [15:0] s1_3;wire   s2_1;wire   [15:0] s2_2;wire   [15:0] s2_3;wire   s3_1;wire   [15:0] s3_2;wire   [15:0] s3_3;wire   s4_1;wire   [15:0] s4_2;wire   [15:0] s4_3;cf_fft_1024_8_23 s1 (clock_c, s3_1, s3_2, s3_3, i4, i5, s1_1, s1_2, s1_3);cf_fft_1024_8_6 s2 (clock_c, s1_1, s1_2, s1_3, i4, i5, s2_1, s2_2, s2_3);cf_fft_1024_8_5 s3 (clock_c, s4_1, s4_2, s4_3, i4, i5, s3_1, s3_2, s3_3);cf_fft_1024_8_2 s4 (clock_c, i1, i2, i3, i4, i5, s4_1, s4_2, s4_3);assign o3 = s2_3;assign o2 = s2_2;assign o1 = s2_1;endmodulemodule cf_fft_1024_8_2 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);input  clock_c;input  i1;input  [15:0] i2;input  [15:0] i3;input  i4;input  i5;output o1;output [15:0] o2;output [15:0] o3;wire   [31:0] n1;wire   n2;wire   n3;wire   [7:0] n4;wire   [7:0] n5;wire   [1:0] n6;wire   [15:0] n7;wire   [15:0] n8;wire   [15:0] n9;wire   [15:0] n10;wire   [15:0] n11;wire   [15:0] n12;wire   s13_1;wire   [31:0] s14_1;wire   s15_1;wire   s15_2;wire   [31:0] s15_3;wire   [8:0] s16_1;wire   s16_2;assign n1 = {i2, i3};assign n2 = s16_1[8];assign n3 = ~n2;assign n4 = {s16_1[7],  s16_1[6],  s16_1[5],  s16_1[4],  s16_1[3],  s16_1[2],  s16_1[1],  s16_1[0]};assign n5 = {n4[0],  n4[1],  n4[2],  n4[3],  n4[4],  n4[5],  n4[6],  n4[7]};assign n6 = {s15_2, s15_1};assign n7 = {s15_3[31],  s15_3[30],  s15_3[29],  s15_3[28],  s15_3[27],  s15_3[26],  s15_3[25],  s15_3[24],  s15_3[23],  s15_3[22],  s15_3[21],  s15_3[20],  s15_3[19],  s15_3[18],  s15_3[17],  s15_3[16]};assign n8 = {s15_3[15],  s15_3[14],  s15_3[13],  s15_3[12],  s15_3[11],  s15_3[10],  s15_3[9],  s15_3[8],  s15_3[7],  s15_3[6],  s15_3[5],  s15_3[4],  s15_3[3],  s15_3[2],  s15_3[1],  s15_3[0]};assign n9 = {s14_1[31],  s14_1[30],  s14_1[29],  s14_1[28],  s14_1[27],  s14_1[26],  s14_1[25],  s14_1[24],  s14_1[23],  s14_1[22],  s14_1[21],  s14_1[20],  s14_1[19],  s14_1[18],  s14_1[17],  s14_1[16]};assign n10 = {s14_1[15],  s14_1[14],  s14_1[13],  s14_1[12],  s14_1[11],  s14_1[10],  s14_1[9],  s14_1[8],  s14_1[7],  s14_1[6],  s14_1[5],  s14_1[4],  s14_1[3],  s14_1[2],  s14_1[1],  s14_1[0]};assign n11 = s13_1 ? n8 : n7;assign n12 = s13_1 ? n10 : n9;cf_fft_1024_8_33 s13 (clock_c, n6, i4, i5, s13_1);cf_fft_1024_8_4 s14 (clock_c, s16_2, n1, n2, n5, i4, i5, s14_1);cf_fft_1024_8_3 s15 (clock_c, s16_2, n1, n3, n5, i4, i5, s15_1, s15_2, s15_3);cf_fft_1024_8_24 s16 (clock_c, i1, i4, i5, s16_1, s16_2);assign o3 = n12;assign o2 = n11;assign o1 = s15_1;endmodulemodule cf_fft_1024_8_3 (clock_c, i1, i2, i3, i4, i5, i6, o1, o2, o3);input  clock_c;input  i1;input  [31:0] i2;input  i3;input  [7:0] i4;input  i5;input  i6;output o1;output o2;output [31:0] o3;wire   [7:0] n1;wire   [7:0] n2;reg    [7:0] n3;wire   n4;reg    n5;wire   [7:0] n6;wire   n7;wire   n8;wire   [31:0] n9;reg    [7:0] n9a;reg    [31:0] n9m [255:0];wire   n10;wire   [31:0] n11;reg    [7:0] n11a;reg    [31:0] n11m [255:0];reg    n12;wire   [31:0] n13;wire   n14;wire   s15_1;assign n1 = 8'b00000001;assign n2 = n3 + n1;initial n3 = 8'b00000000;always @ (posedge clock_c)  if (n14 == 1'b1)    n3 <= 8'b00000000;  else if (i5 == 1'b1)    n3 <= n2;assign n4 = ~s15_1;initial n5 = 1'b0;always @ (posedge clock_c)  if (i6 == 1'b1)    n5 <= 1'b0;  else if (i5 == 1'b1)    n5 <= i1;assign n6 = 8'b00000000;assign n7 = n3 == n6;assign n8 = i3 & n4;initial n9a = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1) begin    if (n8 == 1'b1)      n9m[i4] <= i2;    n9a <= n3;  endassign n9 = n9m[n9a];assign n10 = i3 & s15_1;initial n11a = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1) begin    if (n10 == 1'b1)      n11m[i4] <= i2;    n11a <= n3;  endassign n11 = n11m[n11a];initial n12 = 1'b0;always @ (posedge clock_c)  if (i6 == 1'b1)    n12 <= 1'b0;  else if (i5 == 1'b1)    n12 <= n4;assign n13 = n12 ? n11 : n9;assign n14 = i1 | i6;cf_fft_1024_8_30 s15 (clock_c, i1, i5, i6, s15_1);assign o3 = n13;assign o2 = n7;assign o1 = n5;endmodulemodule cf_fft_1024_8_4 (clock_c, i1, i2, i3, i4, i5, i6, o1);input  clock_c;input  i1;input  [31:0] i2;input  i3;input  [7:0] i4;input  i5;input  i6;output [31:0] o1;wire   [7:0] n1;wire   [7:0] n2;reg    [7:0] n3;wire   n4;wire   n5;wire   [31:0] n6;reg    [7:0] n6a;reg    [31:0] n6m [255:0];wire   n7;wire   [31:0] n8;reg    [7:0] n8a;reg    [31:0] n8m [255:0];reg    n9;wire   [31:0] n10;wire   n11;wire   s12_1;assign n1 = 8'b00000001;assign n2 = n3 + n1;initial n3 = 8'b00000000;always @ (posedge clock_c)  if (n11 == 1'b1)    n3 <= 8'b00000000;  else if (i5 == 1'b1)    n3 <= n2;assign n4 = ~s12_1;assign n5 = i3 & n4;initial n6a = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1) begin    if (n5 == 1'b1)      n6m[i4] <= i2;    n6a <= n3;  endassign n6 = n6m[n6a];assign n7 = i3 & s12_1;initial n8a = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1) begin    if (n7 == 1'b1)      n8m[i4] <= i2;    n8a <= n3;  endassign n8 = n8m[n8a];initial n9 = 1'b0;always @ (posedge clock_c)  if (i6 == 1'b1)    n9 <= 1'b0;  else if (i5 == 1'b1)    n9 <= n4;assign n10 = n9 ? n8 : n6;assign n11 = i1 | i6;cf_fft_1024_8_30 s12 (clock_c, i1, i5, i6, s12_1);assign o1 = n10;endmodulemodule cf_fft_1024_8_5 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);input  clock_c;input  i1;input  [15:0] i2;input  [15:0] i3;input  i4;input  i5;output o1;output [15:0] o2;output [15:0] o3;wire   n1;wire   [31:0] n2;reg    n3;reg    n4;reg    n5;reg    n6;wire   [7:0] n7;reg    [7:0] n8;reg    [7:0] n9;reg    [7:0] n10;reg    [7:0] n11;wire   n12;reg    n13;reg    n14;reg    n15;reg    n16;wire   n17;wire   [1:0] n18;wire   [15:0] n19;wire   [15:0] n20;wire   [15:0] n21;wire   [15:0] n22;wire   [15:0] n23;wire   [15:0] n24;wire   [15:0] s25_1;wire   [15:0] s25_2;wire   s26_1;wire   [31:0] s27_1;wire   s28_1;wire   s28_2;wire   [31:0] s28_3;wire   [8:0] s29_1;wire   s29_2;assign n1 = 1'b0;assign n2 = {s25_1, s25_2};initial n3 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n3 <= 1'b0;  else if (i4 == 1'b1)    n3 <= s29_2;initial n4 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n4 <= 1'b0;  else if (i4 == 1'b1)    n4 <= n3;initial n5 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n5 <= 1'b0;  else if (i4 == 1'b1)    n5 <= n4;initial n6 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n6 <= 1'b0;  else if (i4 == 1'b1)    n6 <= n5;assign n7 = {s29_1[8],  s29_1[7],  s29_1[6],  s29_1[5],  s29_1[4],  s29_1[3],  s29_1[2],  s29_1[1]};initial n8 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n8 <= 8'b00000000;  else if (i4 == 1'b1)    n8 <= n7;initial n9 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n9 <= 8'b00000000;  else if (i4 == 1'b1)    n9 <= n8;initial n10 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n10 <= 8'b00000000;  else if (i4 == 1'b1)    n10 <= n9;initial n11 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n11 <= 8'b00000000;  else if (i4 == 1'b1)    n11 <= n10;assign n12 = s29_1[0];initial n13 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n13 <= 1'b0;  else if (i4 == 1'b1)    n13 <= n12;initial n14 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n14 <= 1'b0;  else if (i4 == 1'b1)    n14 <= n13;initial n15 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n15 <= 1'b0;  else if (i4 == 1'b1)    n15 <= n14;initial n16 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n16 <= 1'b0;  else if (i4 == 1'b1)    n16 <= n15;assign n17 = ~n16;assign n18 = {s28_2, s28_1};assign n19 = {s28_3[31],  s28_3[30],  s28_3[29],  s28_3[28],  s28_3[27],  s28_3[26],  s28_3[25],  s28_3[24],  s28_3[23],  s28_3[22],  s28_3[21],  s28_3[20],  s28_3[19],  s28_3[18],  s28_3[17],  s28_3[16]};assign n20 = {s28_3[15],  s28_3[14],  s28_3[13],  s28_3[12],  s28_3[11],  s28_3[10],  s28_3[9],  s28_3[8],  s28_3[7],  s28_3[6],  s28_3[5],  s28_3[4],  s28_3[3],  s28_3[2],  s28_3[1],  s28_3[0]};assign n21 = {s27_1[31],  s27_1[30],  s27_1[29],  s27_1[28],  s27_1[27],  s27_1[26],  s27_1[25],  s27_1[24],  s27_1[23],  s27_1[22],  s27_1[21],  s27_1[20],  s27_1[19],  s27_1[18],  s27_1[17],  s27_1[16]};assign n22 = {s27_1[15],  s27_1[14],  s27_1[13],  s27_1[12],  s27_1[11],  s27_1[10],  s27_1[9],  s27_1[8],  s27_1[7],  s27_1[6],  s27_1[5],  s27_1[4],  s27_1[3],  s27_1[2],  s27_1[1],  s27_1[0]};assign n23 = s26_1 ? n20 : n19;assign n24 = s26_1 ? n22 : n21;cf_fft_1024_8_39 s25 (clock_c, i2, i3, n1, i4, i5, s25_1, s25_2);cf_fft_1024_8_33 s26 (clock_c, n18, i4, i5, s26_1);cf_fft_1024_8_29 s27 (clock_c, n2, n6, n11, n16, i4, i5, s27_1);cf_fft_1024_8_28 s28 (clock_c, n2, n6, n11, n17, i4, i5, s28_1, s28_2, s28_3);cf_fft_1024_8_24 s29 (clock_c, i1, i4, i5, s29_1, s29_2);assign o3 = n24;assign o2 = n23;assign o1 = s28_1;endmodulemodule cf_fft_1024_8_6 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);input  clock_c;input  i1;input  [15:0] i2;input  [15:0] i3;input  i4;input  i5;output o1;output [15:0] o2;output [15:0] o3;wire   s1_1;wire   [15:0] s1_2;wire   [15:0] s1_3;wire   s2_1;wire   [15:0] s2_2;wire   [15:0] s2_3;wire   s3_1;wire   [15:0] s3_2;wire   [15:0] s3_3;wire   s4_1;wire   [15:0] s4_2;wire   [15:0] s4_3;wire   s5_1;wire   [15:0] s5_2;wire   [15:0] s5_3;wire   s6_1;wire   [15:0] s6_2;wire   [15:0] s6_3;wire   s7_1;wire   [15:0] s7_2;wire   [15:0] s7_3;wire   s8_1;wire   [15:0] s8_2;wire   [15:0] s8_3;cf_fft_1024_8_21 s1 (clock_c, s2_1, s2_2, s2_3, i4, i5, s1_1, s1_2, s1_3);cf_fft_1024_8_19 s2 (clock_c, s3_1, s3_2, s3_3, i4, i5, s2_1, s2_2, s2_3);cf_fft_1024_8_17 s3 (clock_c, s4_1, s4_2, s4_3, i4, i5, s3_1, s3_2, s3_3);cf_fft_1024_8_15 s4 (clock_c, s5_1, s5_2, s5_3, i4, i5, s4_1, s4_2, s4_3);cf_fft_1024_8_13 s5 (clock_c, s6_1, s6_2, s6_3, i4, i5, s5_1, s5_2, s5_3);cf_fft_1024_8_11 s6 (clock_c, s7_1, s7_2, s7_3, i4, i5, s6_1, s6_2, s6_3);cf_fft_1024_8_9 s7 (clock_c, s8_1, s8_2, s8_3, i4, i5, s7_1, s7_2, s7_3);cf_fft_1024_8_7 s8 (clock_c, i1, i2, i3, i4, i5, s8_1, s8_2, s8_3);assign o3 = s1_3;assign o2 = s1_2;assign o1 = s1_1;endmodulemodule cf_fft_1024_8_7 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);input  clock_c;input  i1;input  [15:0] i2;input  [15:0] i3;