module i2c_cmd_7128(clk,rst,rom_data,busy,
               rom_addr,i2c_data_t,cmd_stop,cmd_start,cmd_send,
               execute,i2c_w_finish
               );
//Io defination
input          clk,rst,busy;
input [7:0]    rom_data;

output         cmd_stop,cmd_start,cmd_send,execute,i2c_w_finish;
output[6:0]    rom_addr;
output[7:0]    i2c_data_t;



reg            cmd_stop,cmd_start,cmd_send,execute,i2c_w_finish;
reg[6:0]       rom_addr;
reg[7:0]       i2c_data_t;

//Internal Reg
parameter      GEN_S='H1, S_WAIT='H2, 
               SUBADDR='H5, SUBADDR_ACK='H6, DATA='H7, DATA_ACK='H8,
               GEN_P='H9, P_WAIT='HA, IDLE='HB ,I2C_W_OK='HC,HALT='HD,CREATE_CHIP_RST='HE;
reg   [3:0]    STATE;
reg            group_index;


always @ (posedge clk)
begin
if(!rst)
  begin
  STATE<=IDLE;
  cmd_stop<=0;
  cmd_start<=0;
  cmd_send<=0;
  execute<=0;
  rom_addr<='b0;
  i2c_data_t<='b0;
  group_index<='b0;
  i2c_w_finish<=0;
  end
else
  case (STATE)
  IDLE: begin
        STATE<=GEN_S;
        end
  GEN_S:begin
        i2c_data_t<='h88;    //Saa7128 Write Address
        cmd_start<=1;
        execute<=1;
        if(busy)
           STATE<=S_WAIT;
        else
           STATE<=GEN_S;
        end
 S_WAIT:begin
        cmd_start<=0;
        execute<=0;
        if (!busy)
           STATE<=SUBADDR;  //SLAVE_W;
        else
           STATE<=S_WAIT;
        end
 SUBADDR:
        begin
        i2c_data_t<=group_index? 'h43 : 'h26;     //Start of Group Address 
        cmd_send<=1;
        execute<=1;  
        if(busy)
           STATE<=SUBADDR_ACK;
        else
           STATE<=SUBADDR;
        end
 SUBADDR_ACK:
        begin
        cmd_send<=0;
        execute<=0;
        rom_addr<=group_index?  'h43 : 'h26; 
        if (!busy)
           STATE<=DATA;
        else
           STATE<=SUBADDR_ACK;
        end
 DATA:  begin
        i2c_data_t<=rom_data;     //Data
        cmd_send<=1;
        execute<=1;  
        if(busy)
           STATE<=DATA_ACK;
        else
           STATE<=DATA;
        end
 DATA_ACK:
        begin
        cmd_send<=0;
        execute<=0;
        if (!busy)
           begin
           if( ((!group_index) & (rom_addr>='h3A)) | ((group_index) & (rom_addr>='h7F)) ) 
               STATE<=GEN_P;
           else
               begin
               rom_addr<=rom_addr+1;   
               STATE<=DATA;
               end
           end
        else
           STATE<=DATA_ACK;
        end
  GEN_P:begin
        cmd_stop<=1;
        execute<=1;
        if(busy)
           STATE<=P_WAIT;
        else
           STATE<=GEN_P;
        end
 P_WAIT:begin
        cmd_stop<=0;
        execute<=0;
        if (!busy)
           STATE<=I2C_W_OK;
        else
           STATE<=P_WAIT;
        end

 I2C_W_OK:
        begin
        if (group_index)
           begin
           STATE<=HALT;
           end
        else
           begin
           group_index<=1;
           STATE<=GEN_S;
           end 
		end 
 HALT:  begin
        STATE<=HALT;
        i2c_w_finish<=1;
        end
 default: STATE<=IDLE;
 endcase
end

endmodule