?? clockdiv.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
entity clockdiv is
port(
clockin : in std_logic;
clockout : out std_logic );
end clockdiv;
architecture behavioural of clockdiv is
signal clock_int : std_logic;
begin
clockout <= clock_int;
count : process(clockin)
constant MAX : integer := 26666;
variable counter : integer range 0 to max;
begin
if rising_edge(clockin) then
if counter = MAX then
if clock_int = '0' then
clock_int <= '1';
else
clock_int <= '0';
end if;
counter := 0;
else
counter := counter + 1;
end if;
end if;
end process count;
end behavioural;
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