library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library altera;
use altera.maxplus2.all;

--**********************************
entity doudong is
port(
      din,clk:in std_logic;
    
      dout:out std_logic
     );
end doudong;
--****************************************
architecture a of doudong is
signal vcc,d_tmp:std_logic;
signal d0,d1,q0,q1:std_logic;
begin
vcc<='1';--定義為‘1’就好象原理圖中把引腳接高電平，以下使DFF引腳接高電平
d_tmp<=not din;

dff1:dff 
port map( d=>vcc,q=>q0,clk=>clk,clrn=>d_tmp,prn=>vcc);
dff2:dff
port map( d=>vcc,q=>q1,clk=>clk,clrn=>q0,prn=>vcc);

process(clk)
begin
if clk'event and clk='1'then
    d0<=not q1;
    d1<=d0;
   end if;
end process;
dout<=not(d1 and not d0);
end a;