LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cnt2v is
 port(clk : in std_logic;
       s : out std_logic_vector(1 downto 0));
end;
architecture a of cnt2v is
signal reset : std_logic;
signal q : std_logic_vector(1 downto 0);
begin 
  process(clk)
   begin
     if reset='1'then
       q<="00";
     elsif clk'event and clk='1' then
        q<=q+1;
     end if;
    end process;
   ReSeT <= '1' WHEN Q=3  ELSE	  
		 '0';
   s<=q;
end a;