LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY GGG IS
PORT(d0,d1,sel:IN BIT;
q:OUT BIT);
END GGG;
ARCHITECTURE connect OF GGG IS
SIGNAL tmp:BIT;
BEGIN
cale:PROCESS(d0,d1,sel)
VARIABLE tmp1,tmp2,tmp3:BIT;
BEGIN
tmp1:=d0 AND sel;
tmp2:=d1 AND (NOT sel);
tmp3:=tmp1 OR tmp2;
tmp<=tmp3;
q<=tmp AFTER 5 NS;
END PROCESS;
END connect;