--4dff1--shfit-register--{for--generate}--
--*****************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--**********************************
ENTITY sh_reg IS
  		PORT(
		a,clk: IN	std_logic;
				b: OUT	std_logic);
END ;
--**********************************
ARCHITECTURE rtl OF sh_reg IS
------------------------------------
component dff1
 PORT(
		d,clk: IN	std_logic;
				q: OUT	std_logic);
  end component;
-------------------------------------------
   signal x:  std_logic_vector(0 to 4);
   	BEGIN
      x(0)<=a;
---------------------------------------------
    register1:for i in 0 to 3 generate

      dfx:dff1 port map (x(i), clk ,x(i+1));
    end generate;
------------------------------------------------

           b<= x(4);
end rtl;