library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port (data :in std_logic_vector (7 downto 0);
      a,clk,clr,en :in std_logic;
      mm :out std_logic_vector (7 downto 0));
end;
architecture AA of counter is
signal hold: std_logic_vector (7 downto 0);
begin
process(clk)
 variable change :std_logic_vector (7 downto 0);
begin

if (clk'event and clk='1') then
if clr='0' then
change:="00000000";
elsif en='1' then

if a='1' then
change:=change+data;
if ((change(3)='1') and ((change(2)='1') or (change(1)='1'))) or (not(hold(7 downto 4)=change(7 downto 4)-data(7 downto 4))) then
change:=change+6;
end if;
if ((change(7)='1') and ((change(6)='1') or (change(5)='1'))) then
change:="00000000";
end if;

else
change:=change-data;
if ((change(3)='1') and ((change(2)='1') or (change(1)='1'))) or (not(hold(7 downto 4)=change(7 downto 4)-data(7 downto 4)))  then
change:=change-6;
end if;
if ((change(7)='1') and ((change(6)='1') or (change(5)='1'))) then
change:="00000000";
end if;

end if;

end if;


end if;

mm<=change;
hold<=change;
end process;
end aa;