LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE work.roms.ALL;

ENTITY waveform IS
		PORT(clock: IN std_logic;
             waves:out  rom_range);
END waveform ;
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ARCHITECTURE beh OF waveform IS
 signal step:  rom_range;
 BEGIN 
    PROCESS(clock)
     BEGIN
       if (clock'event and clock='1')then
          if step=rom_range'high then
               step<=rom_range'low;
             else
          step<=step+1;
           end if;
       end if;
     end process;
      waves<=step;
  end beh;