LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY ls160 IS PORT(data: in std_logic_vector(3 downto 0);
          clk,ld,p,t,clr:in std_logic;
		   count: buffer std_logic_vector(3 downto 0);
           tc:out std_logic);
END ls160;

ARCHITECTURE behavior OF ls160 IS
BEGIN  
tc<='1' when (count="1001" and p='1' and t='1' and ld='1' and clr='1') else '0';
 
cale:
 process(clk,clr,p,t,ld)
   begin
     if(rising_edge(clk)) then
      if(clr='1')then
       if(ld='1')then
        if(p='1')then
         if(t='1')then
          if(count="1001")then
           count<="0000";
          else 
           count<=count+1;
          end if;
         else 
          count<=count;
         end if;
        else
         count<=count;
        end if;
       else
         count<=data;
       end if;
      else 
       count<="0000";
      end if;   
    end if;
 end process cale;      
END behavior;