library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity  adder4 is 
port(a,b:in std_logic_vector(3 downto 0);
      ci:in std_logic;
     sum:out std_logic_vector(4 downto 0));
end adder4;

ARCHITECTURE maxpld OF adder4 IS
signal halfadd		:std_logic_vector(4 downto 0);
BEGIN
    halfadd<=('0'&a)+('0'&b);
    sum<=halfadd when ci='0' else halfadd+1;
END maxpld;