library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package res_pack is
function res_func(data : in bit_vector)return bit;
end;
package body res_pack is
function res_func(data:in bit_vector) return bit is
begin
 for i in data'range loop
if data(i)='0' then
return'0';
end if;
end loop;
return'1';
end;
end;
use work.res_pack.all;
entity wand_vhdl is
port(x,y:in bit;z:out resolved_bit);
end wand_vhdl;
ARCHITECTURE wand OF wand_vhdl   IS
BEGIN
z<=x;
z<=y;
end wand;