LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
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ENTITY cnt6 IS
		PORT(clk:in  std_logic;
             ENA: IN std_logic;
             clr:in std_logic;             
              CQ: buffer  std_logic_vector(3 downto 0);
             cARRY_OUT:out  std_logic);

END ;
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ARCHITECTURE A OF cnt6 IS
 BEGIN 
  cARRY_OUT<='1'when (CQ="0101" and ENA='1')else '0';
  PROCESS(CLK,clr)
     BEGIN
       IF(clr='0')THEN
          CQ<="0000";
         elsif (clk'event and clk='1')then
           IF(ENA='1')THEN
               if(CQ=5)then
                 CQ<="0000";
                  else
                   CQ<=CQ+1;
               end if;
         end if;
       end if;
      end process;
  end A;