LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--------------------
ENTITY MB1 IS
		PORT(clk:in  std_logic;
             ENA: IN std_logic;
             clr:in std_logic 
               
                     );

END ;
-----------------------------
ARCHITECTURE A OF MB1 IS
COMPONENT clkgen
     PORT (
            clk : IN STD_LOGIC;
           newclk : OUT  STD_LOGIC
          );
END COMPONENT;
COMPONENT CNT10
		PORT(clk:in  std_logic;
             ENA: IN std_logic;
             clr:in std_logic;             
              CQ: buffer  std_logic_vector(3 downto 0);
             cARRY_OUT:out  std_logic);
END COMPONENT;
COMPONENT CNT6
		PORT(clk:in  std_logic;
             ENA: IN std_logic;
             clr:in std_logic;             
              CQ: buffer  std_logic_vector(3 downto 0);
             cARRY_OUT:out  std_logic);
END COMPONENT;


signal  Q1,q2,Q3,Q4,Q5,Q6:  STD_LOGIC_VECTOR(3 DOWNTO 0);
signal  NEWCLK,CARRY_OUT1,CARRY_OUT2,CARRY_OUT3,CARRY_OUT4,CARRY_OUT5,CARRY_OUT6,CARRY_OUT7:  std_logic;
    BEGIN 
    U1: clkgen PORT MAP(CLK,NEWCLK);
    U2:CNT10      PORT MAP(NEWCLK,ENA,CLR,Q1,cARRY_OUT1);
    U3:CNT10      PORT MAP(cARRY_OUT1,ENA,CLR,Q2,cARRY_OUT2);
    U4:CNT10      PORT MAP(cARRY_OUT2,ENA,CLR,Q3,cARRY_OUT3);
    U5:CNT6      PORT MAP(cARRY_OUT3,ENA,CLR,Q4,cARRY_OUT4);
    U6:CNT10      PORT MAP(cARRY_OUT5,ENA,CLR,Q5,cARRY_OUT6);
    U7:CNT6      PORT MAP(cARRY_OUT6,ENA,CLR,Q6,cARRY_OUT7);
  end A;