--與非門數(shù)據(jù)流描述                   

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--***************
ENTITY and2_1 IS
		PORT(
		a,b: IN	std_logic;
				y: OUT	std_logic);
END and2_1;
--*****************
ARCHITECTURE rtl OF and2_1 IS
begin
   y<=not(a and b);
end rtl;