LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY and2p62 IS
		PORT(
		d0, d1,sel: IN	bit;
				q: OUT	bit);
END and2p62;
ARCHITECTURE struct OF and2p62 IS
component and2_comp
     port(a,b:in bit;
           c:out bit);
     end component;
component or2_comp
     port(a,b:in bit;
           c:out bit);
     end component;
component inv_comp
     port(a:in bit;
           c:out bit);
     end component;
signal aa,ab,nsel:bit;
	BEGIN
	u1:inv_comp port map(sel,nsel);
    u2:and2_comp port map(nsel,d1,ab);
    u3:and2_comp port map(d0,sel,aa);
    u4:or2_comp port map(aa,ab,q);

END struct;