library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY mul4 IS
	PORT(
		clk,reset	: IN	STD_LOGIC;
		a,b			: IN	STD_LOGIC_VECTOR(3 downto 0);
		resultout		: OUT	STD_LOGIC_VECTOR(7 downto 0));
END mul4;
ARCHITECTURE a OF mul4 IS
signal result,shiftresult: STD_LOGIC_VECTOR(7 downto 0);
signal temp,temp2:STD_LOGIC_VECTOR(3 downto 0);
signal count:STD_LOGIC_VECTOR(1 downto 0);

BEGIN
temp<= a when count & b(2)="111" or count & b(1)="101" or count & b(0)="011" else
		"0000";		
temp2<= a when b(3)='1' else "0000";	
shiftresult<=result(6 downto 0) & '0';
clklabel:
PROCESS (clk,reset)
BEGIN
IF reset='1' THEN
    result<="0000" & temp2;
	count<="11";
ELSIF clk'event and clk='1' THEN
   IF count="00" then  result<=result; count<="00";
   ELSE result<=shiftresult+temp;   count<=count-1;END IF;

END IF;
END PROCESS clklabel;
resultout<=result;
END a;