library ieee;
use ieee.std_logic_1164.all;
entity ex is
port(a,b,c: in std_logic;
        data: in std_logic_vector(1 downto 0);
        q: out std_logic);
end ex;
architecture rtl of ex is
begin 
  q<=a when data="00" else
     b when data="11" else
     c;
end;