library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pros_com is
port(event_a:in bit);
end pros_com;
architecture catch_ball of pros_com is
signal to_a,to_b: bit :='0';
begin
  a:
  process(event_a,to_a)
   begin
    if(event_a'event and event_a='1')then
     to_b<='1' after 20 ns;
           to_b<='0' after 30 ns;
     end if;
end process a;
b:
 process(to_b)
  begin
   if(to_b'event and to_b='1')then
    to_a<='1' after 10 ns;
          to_a<='0' after 20 ns;
   end if;
end process b;
end catch_ball;