-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux61 is
 port(a,b,c,d,e,f : in std_logic_vector(3 downto 0);
       sel : in std_logic_vector(2 downto 0);
       q: OUT std_logic_vector(3 downto 0));
end;
architecture a of mux61 is
begin 
  process(a,b,c,d,e,f,sel)
   begin
    case sel is
    when "000"=>q<=a;
    when "001"=>q<=b;
    when "010"=>q<=c;
    when "011"=>q<=d;
    when "100"=>q<=e;
    when "101"=>q<=f;
    when others=>null;
    end case;
    end process;
    end a;